STV3550 datasheet(73/144 Pages) STMICROELECTRONICS

73 / 144 page

CPU and System Management Functional Description

STV3550

73/144

6.3.9.2 SDRAM Requirements

Time is expressed in number of STV3550 system clock cycles, with the SDRAM clock being the

same as the STV3550 system clock.

●

SDRAM size between 16Mbit and 256 Mbit

●

2 or 4 DRAM banks per SDRAM device

●

up to 4096 pages per DRAM bank

●

128 to 4096 data word per page

●

16 bits or 32 bits data word size

●

RAS to CAS between 1 and 8 cycles

●

CAS latency between 1 and 8 cycles

●

Write Recovery Time between 1 and 7 clock cycles

●

Precharge Time between 1 and 16 cycles

●

Refresh Period between 8 and 4096 cycles

●

Refresh Time between 1 and 32 cycles

●

Bus Release Time between 1 and 4 cycles

●

Burst Length of 1 and Sequential Burst Capability

●

SDRAM access cycle frequency up to 100 MHz

Table 20: SDRAM Commands

Command

Strobes state

Mode bits

Address

Notes

NOT_RAS

NOT_CAS

RD_NOT_

Bank Select

(ADDR[16],

ADDR[15])

ADDR[10]

AP1

1. Address bit 10 is also known as the Auto Precharge bit.

ADDR

[11:0]

Precharge

all

Used to close pages after

a burst in simple page

mode.

Row

Activate

1/0

Row

addresses

Opens a page (Row

active)

Write

100

1/0

Column

addresses

Writes data words (uses

NOT_BE to mask data

bytes)

Read

1/0

Col addr

Reads data words

Mode

Set

1/0

Mode data

Done once only at

start -up

CBR

Refresh

CBR style refresh (Auto

Refresh)

Operation

NOP is performed

between commands

such as Row Activate

and Read

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