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STV3550 数据表(PDF) 7 Page - STMicroelectronics

部件名 STV3550
功能描述  LCD and Matrix Display TV Processor
PDF  144 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV3550 数据表(HTML) 7 Page - STMicroelectronics

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General Information
STV3550
7/144
1
General Information
1.1
Introduction
This integrated circuit (IC) is dedicated to flat panel display TV chassis. Combined with a digital
multi-standard video decoder (STV2310) delivering an ITU-R BT.601/656 video stream, it provides
a cost-effective, high-performance solution for plasma or LCD TV applications. The STV3550
includes an up-converter, a 32-bit ST20 CPU core with all peripherals required for controlling the TV
chassis. Teletext data is extracted from the incoming stream and decoded by the CPU. An
embedded On-Screen Display (OSD) generator delivers the text and graphics. The Video Display
Pipeline performs feature box image processing such as picture improvement, horizontal and
vertical rescaling and Temporal Noise Reduction.
The chip operates with an external SDRAM that is used for the field-rate up-conversion and text and
graphic generations.The external SDRAM can be configured as a single bank of 16/64/128 Mb
(16-bit configuration) or a dual bank of 16/64 or 128 Mb (32-bit configuration). Application program
codes are stored in an external Flash memory.
The STV3550 is designed using an 0.18 micron CMOS process and delivered in a 208-pin PQFP
(0.5 mm pitch) package.
The STV3550 completes the Digital IC Core family (STi5xxx, STi7xxx) which offers common CPU
and software platforms based on STMicroelectronics’ 32-bit ST20 CPU core. This device, which is
specifically designed for plasma or LCD TV applications, is completely compatible with the
architecture and software of the STV3500 CTV100-CRT platform that targets CRT-based TV
chassis.
Figure 1: Top Level Diagram
Build-Up
YSI
Video
ST20 Core
H100
SDRAM
SDIN
TNR
HV Filter
8
YCRCB[7:0]
CLK_DATA
CTI
HSYNC
VSYNC
16/32
TV Peripherals
30
I/Os
Flash
Counter
NRESET
Clock
Generator
2D
Block Move
OSD
Pipeline
Pipeline
Block
Time Base
Generator
TV Chassis Control
CSA
Picture
Comp.
Cursor
BG
Plane
EMI4
Compositor
V100
27 MHz
Crystal
Gamma Correction
Digital
Video
Output
Perfect Color
Engine
R
G
B
4- to
RGB Digital
Video
Outputs
10-bit



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