STV3550 datasheet(72/144 Pages) STMICROELECTRONICS

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STV3550

CPU and System Management Functional Description

●

Read and Write

●

CBR Refresh

●

No Operation (NOP)

The STV3550 Memory Interface always accesses SDRAM in Page mode regardless of the burst

length programmed in the Mode Register Set command. It is recommended to use a burst length of

1 to prevent any problems when signal interfaces are shared by the SDRAM and Flash memories.

(For more information, refer to Section 6.3.5: Memory Configurations.)

The STV3550 can be fully parameterized depending on the SDRAM device specification.

Latencies, refresh interval, row/column addresses split, number of SDRAM sub-banks, etc., can be

configured through the control registers.

The STV3550 Memory Interface is compliant with JEDEC and PC100 specifications which

recommend applying a NOP signal for a minimum of 200 µs after the power-on sequence. Once

this period has elapsed, the application software will ask the STV3550 Memory Interface to

Precharge All the banks, to perform eight Refresh commands and to send the Mode Register Set

command. Then the SDRAM device is ready to be used by STV3550 for standard data exchange.

Figure 44: State Table in the STV3550 Memory Interface

Request for

access

Refresh

counter

equals zero

The arcs and states in the state table are a subset of the

possible ones in the SDRAM devices.

Mode

Set

Precharge All/

Refresh

Power-On /

Initialization

CBR

Refresh

Idle

Row

Activate

Read

Write

Precharge

All

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