STV3550 datasheet(69/144 Pages) STMICROELECTRONICS

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CPU and System Management Functional Description

STV3550

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are configured by software via control registers since the STV3550 is always able to boot,

regardless of the memory configuration.

6.3.8

STV3550 Memory Interface Capabilities Regarding Flash Device

6.3.8.1 Supported Flash Commands

The STV3550 is able to read the Flash memory like an asynchronous memory device.

Table 19: Memory Interface Pins

Signal Names

I/O

Size

Comment

FLASH_D[15:0]

I/O

Flash Data bus

The Flash device is always connected to this bus. When a 32-bit data word SDRAM

is used, the Flash Data bus is the first half (LSBs) of the 32-bit bus (the second half

being the SDRAM Data bus (MSBs)).

ADDR[19:0]

Address bus

The Flash device uses this entire bus as a non-multiplexed bus.

The SDRAM devices uses lines 15 and 16 as Bank Activate (BA0 and BA1,

respectively) and lines 0 to 11 for Row or Column Selection (refer to data word size

and addresses dependencies).

When a 32-bit data word SDRAM is connected, lines 18 and 19 supply the Byte

Enable data (NOT_BE[1:0] active low).

NOT_CS_FLASH

Flash Chip Select - Active Low

SDRAM_D[15:0]

I/O

SDRAM Data bus

When a 16-bit data word SDRAM is used, it is connected to this bus.

When a 32-bit data word SDRAM is used, this bus becomes the second half (MSBs)

of the 32-bit bus (the first half (LSBs) being the Flash Data bus).

NOT_CS_SDRAM

SDRAM Chip Select - Active Low

RD_NOT_WR

Read / Write

By default, this is the SDRAM Read/Write signal. When the Flash Write Feature is

activated, this line is also the Flash Read/Write signal.

NOT_BE[1:0]

SDRAM Byte Enable - Active Low

These lines become Byte Enable 3 and 2 (active low) when a 32-bit data word

SDRAM is used.

NOT_RAS

SDRAM Row Address Strobe - Active Low

NOT_CAS

SDRAM Column Address Strobe - Active Low

This line may be used as a Flash Output Enable if the Flash Write Feature is used.

CKOUT_SDRAM

SDRAM Clock

Clock generated by STV3550 for the SDRAM.

CKIN_SDRAM

SDRAM Clock Feedback

This input is used to correctly synchronize the data sent by the SDRAM using the

internal clock of STV3550.

This input is also used by the DLL embedded in the STV3550.

Total Number of

Pins

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