STV3550 datasheet(60/144 Pages) STMICROELECTRONICS

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STV3550

5.4.2

Vsync Output Capability

In both cases we can select the output signal polarity, with a dedicated register bit.

case i_vsync = vs_pad

The VSYNC output is in the ‘clk_vtg’ domain. The pulse size is adjusted by the VTG block.

case i_vsync = vs_rst_100_dac (clk_dac domain - basic mode)

The VSYNC output pad is in the ‘clk_dac’ domain. We could delay the first edge (214-1 clock period)

and we could adjust the pulse width (216-1 clock period).

5.4.3

Hsync Output Capability

The Hsync source choice is fully independent of the Vsync choice. The user must take care to keep

the two choices in a consistent state.

In both cases we could select the output signal polarity, with a dedicated register bit.

case i_hsync = hs_pad

In the case of master mode with the Digital Video Scan, we can choose the H_ref signal as the

STV3550 HSYNC output. This signal is in the ‘clk_vtg’ domain. The Pulse size is controlled by the

VTG block.

In the case of slave mode with the Digital Video Scan, we can choose the H_gen signal as the

STV3550 HSYNC output. This signal is in the ‘clk_dac’ domain. The Pulse size is controlled by the

VTG block.

case i_hsync = hs_pix

The HSYNC output pad is in the ‘clk_dac’ domain. We could delay the first edge (212-1 clock period)

and we could adjust the pulse width (28 clock period).

5.4.4

Csync Output Capability

In the Csync mode the Hsync output PAD is replaced by the Csync output signal.

The Csync signal is the Hsync signal with a polarity inverted when the vsync signal is active.

We could select the Csync polarity with the Hsync polarity register.

5.4.5

RGB Output

We could select the Digital Video Output signal polarity. We have to take two cases into account:

Output all of the signal with a dedicated pin:

Pad

clk_dac

RGB

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