RA4M3 datasheet(37/92 Pages) RENESAS

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Table 2.20

Timing of recovery from low power modes (2 of 2)

Parameter

Symbol

Min Typ

Max

Unit Test conditions

Recovery time from

Deep Software

Standby mode

DPSBYCR.DEEPCUT[1] = 0 and

DPSWCR.WTSTS[5:0] = 0x0E

tDSBY

—

0.38

0.54

Figure 2.15

DPSBYCR.DEEPCUT[1] = 1 and

DPSWCR.WTSTS[5:0] = 0x19

tDSBY

—

0.55

0.73

Wait time after cancellation of Deep Software Standby mode

tDSBYWT

—

tcyc

Recovery time from

Software Standby

mode to Snooze

mode

High-speed mode when system clock source is

HOCO (20 MHz)

tSNZ

—

35*12 70*12 μs

Figure 2.16

High-speed mode when system clock source is

MOCO (8 MHz)

tSNZ

—

11*12 14*12 μs

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be

determined with the following equation:

Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators -

tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC

module stop))

Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the

greatest value of the internal clock division setting is 1.

Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest

value of the internal clock division setting is 4.

Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and

the greatest value of the internal clock division setting is 1.

Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest

value of the internal clock division setting is 4.

Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.

Note 7. The LOCO frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.

Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.

Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.

Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.

Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.

Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs

(maximum).

Note 13. The recovery time can be calcurated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the fol-lowing

value and equation. For n, the greatest value is selected from among the internal clock division settings.

Wakeup time TYP

MAX

Unit

tSBYOSCWT

tSBYSEQ

tSBYOSCWT

tSBYSEQ

tSBYMC

(MSTS[7:0]*32 + 3) /

0.262

35 + 18 / fICLK + 4n / fMAIN

(MSTS[7:0]*32 + 14 /

0.236

62 + 18 / fICLK + 4n / fMAIN

µs

tSBYPC

(MSTS[7:0]*32 + 34) /

0.262

35 + 18 / fICLK + 4n / fPLL

(MSTS[7:0]*32 + 45) /

0.236

62 + 18 / fICLK + 4n / fPLL

µs

tSBYEX

35 + 18 / fICLK + 4n / fEXMAIN 62

62 + 18 / fICLK + 4n / fEXMAIN µs

tSBYPE

135

35 + 18 / fICLK + 4n / fPLL

192

62 + 18 / fICLK + 4n / fPLL

µs

tSBYSC

35 + 18 / fICLK + 4n / fSUB

62 + 18 / fICLK + 4n / fSUB

µs

tSBYLO

35 + 18 / fICLK + 4n / fLOCO

62 + 18 / fICLK + 4n / fLOCO

µs

tSBYHO

35 + 18 / fICLK + 4n / fHOCO

62 + 18 / fICLK + 4n / fHOCO

µs

tSBYPH

140

35 + 18 / fICLK + 4n / fPLL

202

62 + 18 / fICLK + 4n / fPLL

µs

tSBYMO

35 + 18 / fICLK + 4n / fMOCO

62 + 18 / fICLK + 4n / fMOCO

µs

RA4M3 Datasheet

2. Electrical Characteristics

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

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