RA4M3 datasheet(87/92 Pages) RENESAS

87 / 92 page

Table 3.1

Peripheral base address (3 of 3)

Name

Description

Base address

FLAD

Data Flash

0x407F_C000

FACI

Flash Application Command Interface

0x407F_E000

QSPI

Quad-SPI

0x6400_0000

Note:

Name = Peripheral name

Description = Peripheral functionality

Base address = Lowest reserved address or address used by the peripheral

3.2

Access Cycles

This section provides access cycle information for the I/O registers described in this manual.

● Registers are grouped by associated module.

● The number of access cycles indicates the number of cycles based on the specified reference clock.

● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations

cannot be guaranteed.

● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization

cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio

between ICLK and PCLK.

● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always

constant.

● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided

clock synchronization cycles.

● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.

Note:

This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the

external memory or bus access from other bus masters such as DTC or DMAC.

Table 3.2

Access cycles (1 of 3)

Peripherals

Address

Number of access cycles

ICLK = PCLK

ICLK > PCLK*1

Cycle

Unit

Related function

From

Read

Write

Read

Write

RMPU, TZF,

SRAM, BUS,

DMACn, DMA,

DTC, ICU

0x4000_0000

0x4000_6FFF

ICLK

Renesas Memory

Protection Unit,

TrustZone Filter,

SRAM Control, BUS

Control, Direct

memory access

controller n, DMAC

Module Activation,

DTC Control Register,

Interrupt Controller

CACHE

0x4000_7000

0x4000_7FFF

ICLK

CACHE

CPSCU, DBG,

FCACHE

0x4000_8000

0x4001_CFFF

ICLK

CPU System Security

Control Unit, Debug

Function, Flash Cache

SYSC

0x4001_E000

0x4001_E3FF

ICLK

System Control

SYSC

0x4001_E400

0x4001_E5FF

5 to 8

PCLKB

System Control

PORTn, PFS

0x4008_0000

0x4008_0FFF

2 to 5

2 to 4

PCLKB

Port n Control

Registers, Pmn Pin

Function Control

RA4M3 Datasheet

Appendix 3. I/O Registers

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

Page 87 of 92

RA4M3 数据表(PDF) 87 Page - Renesas Technology Corp

RA4M3 数据表(HTML) 87 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载

链接网址

RA4M3 数据表(PDF) 87 Page - Renesas Technology Corp

RA4M3 数据表(HTML) 87 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表 下载

链接网址

数据表下载