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RA4M3 数据表(PDF) 57 Page - Renesas Technology Corp

部件名 RA4M3
功能描述  Armv8-M architecture with the main extension
PDF  92 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RA4M3 数据表(HTML) 57 Page - Renesas Technology Corp

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Table 2.30
IIC timing (2)
Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
Test conditions
IIC
(Fast-mode+)
ICFER.FMPE = 1
SCL input cycle time
tSCL
6 (12) × tIICcyc +
240
—
ns
Figure 2.43
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 120 —
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 120 —
ns
SCL, SDA rise time
tSr
—
120
ns
SCL, SDA fall time
tSf
20 × (external
pullup voltage/
5.5V)
120
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time when
wakeup function is disabled
tBUF
3 (6) × tIICcyc + 120 —
ns
SDA input bus free time when
wakeup function is enabled
tBUF
3 (6) × tIICcyc + 4 ×
tPcyc + 120
—
ns
Start condition input hold time
when wakeup function is disabled
tSTAH
tIICcyc + 120
—
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1 (5) × tIICcyc +
tPcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
Data input setup time
tSDAS
tIICcyc + 30
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
550
pF
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note:
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 1. Cb indicates the total capacity of the bus line.
RA4M3 Datasheet
2. Electrical Characteristics
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 57 of 92



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