RA4M3 datasheet(4/92 Pages) RENESAS

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Table 1.7

Timers (2 of 2)

Feature

Functional description

Low power Asynchronous General

Purpose Timer (AGT)

The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used

for pulse output, external pulse width or period measurement, and counting external events. This

timer consists of a reload register and a down counter. The reload register and the down counter

are allocated to the same address, and can be accessed with the AGT register.

Realtime Clock (RTC)

The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode,

that are used by switching register settings. For calendar count mode, the RTC has a 100-year

calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count

mode, the RTC counts seconds and retains the information as a serial value. Binary count mode

can be used for calendars other than the Gregorian (Western) calendar.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow

interrupt.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the

MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer

operates with an independent, dedicated clock source, it is particularly useful in returning the

MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT

can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value

in the registers.

Table 1.8

Communication interfaces (1 of 2)

Feature

Functional description

Serial Communications Interface (SCI)

The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous

serial interfaces:

● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

● 8-bit clock synchronous interface

● Simple IIC (master-only)

● Simple SPI

● Smart card interface

● Manchester interface

● Extended Serial interface

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol. SCIn (n = 0, 3, 4, 9) has FIFO buffers to enable continuous and full-duplex

communication, and the data transfer speed can be configured independently using an on-chip

baud rate generator.

I2C bus interface (IIC)

The I2C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset

of the NXP I2C (Inter-Integrated Circuit) bus interface functions.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial

communications with multiple processors and peripheral devices.

Control Area Network (CAN)

The Controller Area Network (CAN) module uses a message-based protocol to receive and

transmit data between multiple slaves and masters in electromagnetically noisy applications. The

module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32

mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO

modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN

module requires an additional external CAN transceiver.

USB 2.0 Full-Speed module (USBFS)

The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.

The module supports full-speed and low-speed (host controller only) transfer as defined in

Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has

buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned

any endpoint number based on the peripheral devices used for communication or based on your

system.

Quad Serial Peripheral Interface (QSPI) The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM

(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has

an SPI-compatible interface.

RA4M3 Datasheet

1. Overview

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

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