RA4M3 datasheet(44/92 Pages) RENESAS

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tTXD

tRXS tRXH

TXDn

RXDn

SCKn

Note:

n = 0 to 4, 9

Figure 2.27

SCI input/output timing in clock synchronous mode

Table 2.25

SCI timing (2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple SPI

SCK clock cycle output (master)

tSPcyc

65536

tPcyc

Figure 2.28

SCK clock cycle input (slave)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall time

tSPCKr, tSPCKf

—

Data input setup time

master

tSU

—

Figure 2.29 to Figure

2.32

slave

—

Data input hold time

—

SS input setup time

tLEAD

—

tSPcyc

SS input hold time

tLAG

—

tSPcyc

Data output delay

master

tOD

—

slave

—

Data output hold time

tOH

-5

—

Data rise and fall time

tDr, tDf

—

SS input rise and fall time

tSSLr, tSSLf

—

Slave access time

tSA

—

3 × tPcyc + 25

Figure 2.32

Slave output release time

tREL

—

3 × tPcyc + 25

Note:

tPcyc: PCLKA cycle.

RA4M3 Datasheet

2. Electrical Characteristics

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

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