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RA4M3 数据表(PDF) 59 Page - Renesas Technology Corp

部件名 RA4M3
功能描述  Armv8-M architecture with the main extension
PDF  92 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RA4M3 数据表(HTML) 59 Page - Renesas Technology Corp

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Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.
SSIBCK0
tHC
tO, tI
tLC
tRC
tFC
Figure 2.44
SSIE clock input/output timing
GTIOC2A,
AUDIO_CLK
(input)
tEXH
tEXL
tEXr
tEXcyc
tEXf
1/2 VCC
Figure 2.45
Clock input timing
tSR
tHR
tDTR
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)
SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)
Figure 2.46
SSIE data transmit and receive timing when SSICR.BCKP = 0
RA4M3 Datasheet
2. Electrical Characteristics
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 59 of 92



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