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VG6640 数据表(PDF) 107 Page - STMicroelectronics |
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VG6640 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 126 page ![]() DocID023597 Rev 11 107/126 VG6640, VD6640 Application 125 11.3.2 Power-down procedure Table 61. Power-down sequence timing constraints Symbol C Parameter Minimum Maximum Units t8 Last I2C transaction to frame end(1) 1. The power down sequence is triggered by the I2C power down request, however the power down sequence will only start after the end of the frame when all active data has been transferred to the output interface. Once complete, the CSI-2 data signals enter LP11. The CSI-2 clock will enter LP11 with a delay of 5 µs (corresponding to Tclk_post + Tclk_trail) after the data signals. The device will remain in LP11 unless the sensor restarts streaming or RESET_N is pulled low. 1frames t9 Frame end to RESET_N falling 512 clock cycles t10 RESET_N falling to XSHUTDOWN falling ∞ ms t11 RESET_N falling to EXTCLK_XTAL1 stopping ∞ ms t12 VDIG falling to VANA falling VANA and VDIG may fall in any order, the falling edge separation can vary from 0 ns to indefinite t13 VANA falling to VDIG falling |
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