MCP48FVB21 datasheet(28/84 Pages) MICROCHIP

28 / 84 page

MCP48FVBXX

DS20005466A-page 28

 2015 Microchip Technology Inc.

3.1

Positive Power Supply Input (VDD)

VDD is the positive supply voltage input pin. The input

supply voltage is relative to VSS.

The power supply at the VDD pin should be as clean as

possible for a good DAC performance. It is

recommended to use an appropriate bypass capacitor

of about 0.1 µF (ceramic) to ground. An additional

10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate noise present in

application boards.

3.2

Voltage Reference Pin (VREF)

The VREF pin is either an input or an output. When the

DAC’s voltage reference is configured as the VREF pin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

When the DAC’s voltage reference is configured as the

VREF pin, there are two options for this voltage input:

•VREF pin voltage buffered

•VREF pin voltage unbuffered

The buffered option is offered in cases where the

external reference voltage does not have sufficient

current capability to not drop its voltage when

connected to the internal resistor ladder circuit.

When the DAC’s voltage reference is configured as the

device VDD, the VREF pin is disconnected from the

internal circuit.

When the DAC’s voltage reference is configured as the

internal band gap, the VREF pin’s drive capability is

minimal, so the output signal should be buffered.

See Section 5.2, “Voltage Reference Selection” and

3.3

Analog Output Voltage Pin (VOUT)

VOUT is the DAC analog voltage output pin. The DAC

output has an output amplifier. The DAC output range is

dependent on the selection of the voltage reference

source (and potential Output Gain selection). These are:

•Device VDD - The full-scale range of the DAC

output is from VSS to approximately VDD.

•VREF pin - The full-scale range of the DAC output

is from VSS to G  VRL, where G is the gain

selection option (1x or 2x).

• Internal Band Gap - The full-scale range of the

DAC output is from VSS to G  (2  VBG), where G

is the gain selection option (1x or 2x).

In Normal mode, the DC impedance of the output pin is

about 1

. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

, 100 k, or open. The Power-Down Selection bits

settings are shown in Register 4-3 and Table 5-5.

3.4

No Connect (NC)

The NC pin is not connected to the device.

3.5

Ground (VSS)

The VSS pin is the device ground reference.

The user must connect the VSS pin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (printed

circuit board), it is highly recommended that the VSS pin

be tied to the analog ground path or isolated within an

analog ground plane of the circuit board.

3.6

Latch Pin (LAT)/High-Voltage

Command (HVC)

The LAT pin is used to force the transfer of the DAC

allows DAC outputs to be updated at the same time.

The update of the VRxB:VRxA, PDxB:PDxA and

Gx bits are also controlled by the LAT pin state.

The pin is compatible with HVC voltage levels that are

used for the nonvolatile MCP48FEBXX devices.

3.7

SPI - Chip Select Pin (CS)

The CS pin enables/disables the serial interface. The

serial interface must be enabled for the SPI commands

to be received by the device.

Refer to Section 6.2, “SPI Serial Interface” for more

details of SPI Serial Interface communication.

3.8

SPI - Serial Data In Pin (SDI)

The SDI pin is the serial data input pin of the SPI

interface. The SDI pin is used to write the DAC

registers and configuration bits.

Refer to Section 6.2, “SPI Serial Interface” for more

details on SPI Serial Interface communication.

3.9

SPI - Serial Data Out Pin (SDO)

The SDO pin is the serial data output pin of the SPI

interface. The SDO pin is used to read the DAC

registers and configuration bits.

Refer to Section 6.2, “SPI Serial Interface” for more

details on SPI Serial Interface communication.

3.10

SPI - Serial Clock Pin (SCK)

The SCK pin is the serial clock pin of the SPI interface.

The MCP48FVBXX SPI Interface only accepts external

serial clocks.

Refer to Section 6.2, “SPI Serial Interface” for more

details on SPI Serial Interface communication.

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