MCP48FVB21 datasheet(14/84 Pages) MICROCHIP

14 / 84 page

MCP48FVBXX

DS20005466A-page 14

 2015 Microchip Technology Inc.

DC CHARACTERISTICS (CONTINUED)

DC Characteristics

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C

 TA  +125°C (Extended)

Unless otherwise noted, all parameters apply across these specified operating ranges:

VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V

Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF

Typical specifications represent values for VDD = 5.5V, TA = +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

-3 dB Bandwidth

(see B.16 “-3 dB

Bandwidth”

)

—

200

—

kHz

VREF = 2.048V ± 0.1V

VRxB:VRxA = ‘10’, Gx = ‘0’

—100

—

kHz

VREF = 2.048V ± 0.1V

VRxB:VRxA = ‘10’, Gx = ‘1’

Output Amplifier

Minimum Output

Voltage

VOUT(MIN)

—

0.01

—

1.8V

 VDD  5.5V

Output Amplifier’s minimum drive

Maximum Output

Voltage

VOUT(MAX)

—VDD –

0.04

—

1.8V

 VDD  5.5V

Output Amplifier’s maximum drive

Phase Margin

—

Degree

(°)

CL = 400 pF

RL = 

Slew Rate (9)

—

0.44

—

V/µs

RL = 5 k

Short-Circuit Current

ISC

DAC code = Full Scale

Internal Band Gap

Band Gap Voltage

VBG

1.18

1.22

1.26

Band Gap Voltage

Temperature

Coefficient

VBGTC

—15

—

ppm/°C

Operating Range

(VDD)

2.0

—

5.5

VREF pin voltage stable

2.2

—

5.5

VOUT output linear

External Reference (VREF)

Input Range (1)

VREF

VSS

—VDD – 0.04

VRxB:VRxA = ‘11’ (Buffered mode)

VSS

—VDD

VRxB:VRxA = ‘10’ (Unbuffered mode)

Input Capacitance

CREF

—

VRxB:VRxA = ‘10’ (Unbuffered mode)

Total Harmonic

Distortion (1)

THD

—

-64

—

VREF = 2.048V ± 0.1V

VRxB:VRxA = ‘10’, Gx = ‘0’

Frequency = 1 kHz

Dynamic Performance

Major Code

Transition Glitch (see

B.14 “Major-Code

Transition Glitch”

)

—

nV-s

1 LSb change around major carry

7FFh to 800h for 12-bit devices

1FFh to 200h for 10-bit devices

7Fh to 80h for 8-bit devices

Digital Feedthrough

(see B.15 “Digital

Feedthrough”

)

—<10

—

nV-s

Note 1

This parameter is ensured by design.

Note 9

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit

device).

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