MCP48FVB21 datasheet(54/84 Pages) MICROCHIP

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MCP48FVBXX

DS20005466A-page 54

 2015 Microchip Technology Inc.

7.1

Write Command

Write commands are used to transfer data to the

desired memory location (from the Host controller).

Write commands can be structured as either Single or

Continuous.

The format of the command is shown in Figures 7-2

(Single) and 7-3 (Continuous).

A write command to a volatile memory location

changes that location after a properly formatted write

command has been received.

7.1.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

active state (VIL). Typically, the CS pin will be in the

inactive state (VIH) and is driven to the active state

(VIL). The 24-bit Write command (Command Byte

and Data Bytes) is then clocked in on the SCK and

SDI pins. Once all 24 bits have been received, the

specified volatile address is updated. A write will not

occur if the Write command is not exactly 24 clock

pulses. This protects against system issues corrupting

the volatile memory locations.

Figures 7-4 and 7-5 show the waveforms for a single

write (depending on SPI mode).

7.1.2

CONTINUOUS WRITES TO

VOLATILE MEMORY

A continuous write mode of operation is possible when

writing to the device’s volatile memory registers (see

Table 7-3). Figure 7-3 shows the sequence for three

continuous writes. The writes do not need to be to the

same volatile memory address.

FIGURE 7-2:

Write Command - SDI and SDO States.

Note 1:

During device communication, if the

Device Address/Command combination

is invalid or an unimplemented Device

Address

specified,

then

the

MCP48FVBXX will generate a Command

Error state. To reset the SPI state

machine, the CS pin must transition to

the inactive state (VIH).

TABLE 7-3:

VOLATILE MEMORY

ADDRESSES

Address

Single-Channel

Dual-Channel

00h

Yes

01h

Yes

08h

Yes

09h

Yes

0Ah

Yes

00 C

111111111111111111111111 Valid (1)

1111111

0Invalid (2, 3)

Address

Data bits (8, 10, or 12 bits)

SDI

SDO

Command

Note 1:

If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.

12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller

operation (i.e., no data manipulation before transmitting the desired value).

Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)

will be output as ‘1’.

If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition

is cleared (the CS pin is forced to the inactive state).

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