MCP48FVB21 datasheet(67/84 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005466A-page 67

MCP48FVBXX

8.8

Design Considerations

In the design of a system with the MCP48FVBXX

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

8.8.1

POWER SUPPLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of noise sources

on signal integrity. Figure 8-8 illustrates an appropriate

bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as close

(within 4 mm) to the device power pin (VDD) as possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 8-8:

Typical Microcontroller

Connections.

8.8.2

LAYOUT CONSIDERATIONS

Several layout considerations may be applicable to

your application. These may include:

• Noise

• PCB Area Requirements

8.8.2.1

Noise

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP48FVBXX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

boards utilizing a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

capable

providing.

Particularly

harsh

environments may require shielding of critical signals.

Separate digital and analog ground planes are

recommended. In this case, the VSS pin and the ground

pins of the VDD capacitors should be terminated to the

analog ground plane.

8.8.2.2

PCB Area Requirements

In some applications, PCB area is a criteria for device

selection. Table 8-2 shows the typical package

dimensions and area for the 10-lead MSOP package.

VDD

VSS

0.1 µF

SDI

VOUT

VREF

SDO

SCK

Note:

Breadboards and wire-wrapped boards

are not recommended.

TABLE 8-2:

PACKAGE FOOTPRINT (1)

Package

Package Footprint

Type

Code

Dimensions

(mm)

Area (mm2)

Length Width

10 MSOP

3.00

4.90

14.70

Note 1:

Does not include recommended land

pattern

dimensions.

Dimensions

are

typical values.

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