MCP48FVB21 datasheet(47/84 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005466A-page 47

MCP48FVBXX

5.6.1

EXITING POWER-DOWN

When the device exits Power-Down mode, the

following occurs:

• Disabled circuits (op amp, resistor ladder, et al.)

are turned on

• The resistor ladder is connected to selected

reference voltage (VRL)

• The selected pull-down resistor is disconnected

•The VOUT output is driven to the voltage

represented by the volatile DAC Register’s value

and configuration bits

The VOUT output signal will require time as these

circuits are powered-up and the output voltage is driven

to the specified value as determined by the volatile

DAC register and configuration bits.

A write command forcing the PD1:PD0 bits to ‘00’, will

cause the device to exit the power-down mode.

5.7

DAC Registers, Configuration

Bits, and Status Bits

The MCP48FVBXX devices have volatile memory.

Table 4-2 shows the volatile memory and its interaction

due to a POR event.

In the volatile memory, there are five configuration bits,

the DAC registers and two volatile status bits. The

volatile DAC registers will be either 12 bits

(MCP48FVB2X), 10 bits (MCP48FVB1X), or 8 bits

(MCP48FVB0X) wide.

When the device is first powered-up, it automatically

loads the device default values to the volatile memory.

The volatile memory determines the analog output

(VOUT) pin voltage. After the device is powered-up, the

user can update the device memory.

The memory is read and written using an SPI interface.

Refer to Sections 6.0, “SPI Serial Interface Module”

and 7.0, “SPI Commands” for more details on reading

and writing the device’s memory.

bits, and Table 4-2 shows the default factory value of

the device configuration bits after a POR/BOR event.

There is one status bit (the POR bit) which indicates if

the device VDD is above or below the POR trip point.

After a POR event, this bit is a ‘1’. Reading the Gain

Control and System Status register clears this bit (‘0’).

Note:

Since the op amp and resistor ladder were

powered-off (0V), the op amp’s input

voltage (VW) can be considered 0V. There

is a delay (TPDD) between the PD1:PD0

bits updating to ‘00’ and the op amp

driving the VOUT output. The op amp’s

settling time (from 0V) needs to be taken

into account to ensure the VOUT voltage

reflects the selected value.

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