MCP48FVB21 datasheet(30/84 Pages) MICROCHIP

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MCP48FVBXX

DS20005466A-page 30

 2015 Microchip Technology Inc.

4.1.1

POWER-ON RESET

The Power-on Reset is the case where the device VDD

is having power applied to it from the VSS voltage level.

As the device powers up, the VOUT pin will float to an

unknown value. When the device’s VDD is above the

transistor threshold voltage of the device, the output

will start being pulled low. After the VDD is above the

POR/BOR trip point (VBOR/VPOR), the resistor

network’s wiper will be loaded with the POR value

(mid-scale). The volatile memory determines the

analog output (VOUT) pin voltage. After the device is

powered-up, the user can update the device memory.

When the rising VDD voltage crosses the VPOR trip

point (a Power-on Reset event), the following occurs:

• The default DAC register value is latched into

volatile DAC register

• The default configuration bit values are latched

into volatile configuration bits

• POR Status bit is set (‘1’)

• The Reset Delay Timer (tPORD) starts; when the

reset delay timer (tPORD) times out, the SPI serial

interface is operational. During this delay time, the

SPI interface will not accept commands.

• The Device Memory Address pointer is forced to

00h.

The analog output (VOUT) state will be determined by

the state of the volatile configuration bits and the DAC

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

4.1.2

BROWN-OUT RESET

The Brown-out Reset occurs when a device had

power applied to it and that power (voltage) drops

below the specified range.

When the falling VDD voltage crosses the VPOR trip

point (BOR event), the following occurs:

• Serial Interface is disabled

• Device is forced into a Power-Down state

(PDxB:PDxA = ‘11’). Analog circuitry is turned off

• Volatile DAC Register is forced to 000h

• Volatile configuration bits VRxB:VRxA and Gx are

forced to ‘0’

If the VDD voltage decreases below the VRAM voltage,

all volatile memory may become corrupted.

As the voltage recovers above the VPOR/VBOR voltage,

see Section 4.1.1, “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location to become

corrupted.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

FIGURE 4-1:

Power-on Reset Operation.

VPOR

TPORD (50 µs max.)

VDD(MIN)

Normal Operation

BOR reset,

volatile DAC Register = 000h

volatile VRxB:VRxA = 00

Device in

Below

VRAM

Device in

POR state

unknown

state

minimum

operating

voltage

Device in

unknown

state

Device

in power

-down

state

volatile Gx = 0

volatile PDxB:PDxA = 11

VBOR

Volatile memory

retains data value

Volatile memory

becomes corrupted

POR starts Reset Delay Timer.

When timer times out, SPI interface

can operate (if VDD  VDD(MIN))

Default device configuration latched

into volatile configuration bits and

DAC register. POR status bit is set.

POR reset forced active

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