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MCP48FVB21 数据表(PDF) 35 Page - Microchip Technology |
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MCP48FVB21 数据表(HTML) 35 Page - Microchip Technology |
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35 / 84 page ![]() 2015 Microchip Technology Inc. DS20005466A-page 35 MCP48FVBXX Register 4-3 shows the format of the Power-Down Control Register. Each DAC has two bits to control the Power-Down state of the DAC. REGISTER 4-3: POWER-DOWN CONTROL REGISTER (ADDRESS 09h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 Single — — — — — — — — — — — — —(1) —(1) PD0B PD0A Dual — — — — — — — — — — — — PD1B PD1A PD0B PD0A bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown = Single-channel device = Dual-channel device Single Dual bit 15-2 bit 15-4 Unimplemented: Read as ‘0’ bit 1-0 bit 3-0 PDxB-PDxA: DAC Power-Down Control bits (2) 11 =Powered Down - VOUT is open circuit. 10 =Powered Down - VOUT is loaded with a 100 k resistor to ground. 01 =Powered Down - VOUT is loaded with a 1 k resistor to ground. 00 =Normal Operation (Not powered-down) Note 1: Unimplemented bit, read as ‘0’. 2: See Table 5-5 and Figure 5-10 for more details. |
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