| 数据搜索系统,热门电子元器件搜索 |
|
MCP48FVB21 数据表(PDF) 45 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP48FVB21 数据表(HTML) 45 Page - Microchip Technology |
|
45 / 84 page ![]() 2015 Microchip Technology Inc. DS20005466A-page 45 MCP48FVBXX 5.5 Latch Pin (LAT) The Latch pin controls when the volatile DAC Register value is transferred to the DAC wiper. This is useful for applications that need to synchronize the wiper(s) updates to an external event, such as zero crossing or updates to the other wipers on the device. The LAT pin is asynchronous to the serial interface operation. When the LAT pin is high, transfers from the volatile DAC register to the DAC wiper are inhibited. The volatile DAC register value(s) can still be updated. When the LAT pin is low, the volatile DAC register value is transferred to the DAC wiper. Figure 5-8 shows the interaction of the LAT pin and the loading of the DAC wiper x (from the volatile DAC Register x). The transfers are level driven. If the LAT pin is held low, the corresponding DAC wiper is updated as soon as the volatile DAC Register value is updated. FIGURE 5-8: LAT and DAC Interaction. The LAT pin allows the DAC wiper to be updated to an external event as well as have multiple DAC channels/devices update at a common event. Since the DAC wiper x is updated from the Volatile DAC Register x, all DACs that are associated with a given LAT pin can be updated synchronously. If the application does not require synchronization, then this signal should be tied low. Figure 5-9 shows two cases of using the LAT pin to control when the wiper register is updated relative to the value of a sine wave signal. FIGURE 5-9: Example Use of LAT Pin Operation. Note: This allows both the volatile DAC0 and DAC1 registers to be updated while the LAT pin is high, and to have outputs synchronously updated as the LAT pin is driven low. Write Command Register Address Vol. DAC Register x DAC wiper x 16 Clocks LAT SYNC Transfer Serial Shift Reg Data (internal signal) LAT SYNC Transfer Data Comment 11 0 No Transfer 10 0 No Transfer 01 1 Vol. DAC Register x DAC wiper x 00 0 No Transfer Case 1: Zero Crossing of sine wave to update volatile DAC0 register (using LAT pin) Case 2: Fixed Point Crossing of sine wave to update volatile DAC0 register (using LAT pin) Indicates where LAT pin pulses active (volatile DAC0 register updated). |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |