MCP48FVB21 datasheet(40/84 Pages) MICROCHIP

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MCP48FVBXX

DS20005466A-page 40

 2015 Microchip Technology Inc.

5.3

Output Buffer/VOUT Operation

The Output Driver buffers the wiper voltage (VW) of the

Resistor Ladder.

The DAC output is buffered with a low-power, precision

output amplifier (op amp). This amplifier provides a

rail-to-rail output with low offset voltage and low noise.

The amplifier’s output can drive the resistive and

high-capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications. Refer

to Section 1.0, “Electrical Characteristics” for the

specifications of the output amplifier.

Figure 5-5 shows the block diagram of the output driver

circuit.

The user can select the output gain of the output

amplifier. The gain options are:

Gain of 1, with either the VDD or VREF pin used

as reference voltage.

Gain of 2.

Power-down logic also controls the output buffer

operation

(see

Section

5.6,

“Power-Down

Operation”

)

for

additional

information

Power-Down. In any of the three power-down modes,

the op amp is powered-down and its output becomes a

high impedance to the VOUT pin.

Table 5-1 shows the gain bit operation.

FIGURE 5-5:

Output Driver Block Diagram.

5.3.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

configuration bit (see Register 4-4) and the VRL

reference selection (see Section 5.2, “Voltage

Reference Selection”

The volatile G bit value can be modified by:

• POR events

• BOR events

• SPI write commands

Note:

The load resistance must be kept higher

than 5 k

 for stable and expected analog

output (to meet electrical specifications).

TABLE 5-1:

OUTPUT DRIVER GAIN

Gain Bit

Gain

Comment

1—

Limits VREF pin voltages

relative to device VDD voltage.

Gain

VOUT

PD1:PD0

VDD

PD1:PD0

Note 1:

Gain options are 1x and 2x.

(1)

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