DSPIC33EP64GS708 datasheet(23/484 Pages) MICROCHIP

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DS70005258C-page 23

dsPIC33EPXXXGS70X/80X FAMILY

3.0

CPU

The dsPIC33EPXXXGS70X/80X family CPU has a 16-bit

(data) modified Harvard architecture with an enhanced

instruction set, including significant support for Digital

Signal Processing (DSP). The CPU has a 24-bit

instruction word with a variable length opcode field.

The Program Counter (PC) is 23 bits wide and

addresses up to 4M x 24 bits of user program memory

space.

An instruction prefetch mechanism helps maintain

throughput and provides predictable execution. Most

instructions execute in a single-cycle effective execu-

tion rate, with the exception of instructions that change

the program flow, the double-word move (MOV.D)

instruction, PSV accesses and the table instructions.

Overhead-free program loop constructs are supported

using the DO and REPEAT instructions, both of which

are interruptible at any point.

3.1

Registers

The dsPIC33EPXXXGS70X/80X devices have sixteen,

16-bit Working registers in the programmer’s model. Each

of the Working registers can act as a Data, Address or

Address Offset register. The 16th Working register (W15)

operates as a Software Stack Pointer for interrupts and

calls.

In addition, the dsPIC33EPXXXGS70X/80X devices

include four Alternate Working register sets which consist

of W0 through W14. The Alternate Working registers can

be made persistent to help reduce the saving and restor-

ing of register content during Interrupt Service Routines

(ISRs). The Alternate Working registers can be assigned

to a specific Interrupt Priority Level (IPL1 through IPL7) by

configuring the CTXTx<2:0> bits in the FALTREG Config-

uration register. The Alternate Working registers can also

be accessed manually by using the CTXTSWP instruction.

The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT

recent, manually selected Working register sets.

3.2

Instruction Set

The instruction set for dsPIC33EPXXXGS70X/80X

devices has two classes of instructions: the MCU class

of instructions and the DSP class of instructions. These

two instruction classes are seamlessly integrated into the

architecture and execute from a single execution unit.

The instruction set includes many addressing modes and

was designed for optimum C compiler efficiency.

3.3

Data Space Addressing

The base Data Space can be addressed as up to

4K words or 8 Kbytes, and is split into two blocks,

referred to as X and Y data memory. Each memory block

has its own independent Address Generation Unit

(AGU). The MCU class of instructions operates solely

through the X memory AGU, which accesses the entire

memory map as one linear Data Space. Certain DSP

instructions operate through the X and Y AGUs to sup-

port dual operand reads, which splits the data address

space into two parts. The X and Y Data Space boundary

is device-specific.

The upper 32 Kbytes of the Data Space memory map

can optionally be mapped into Program Space (PS) at

any 16K program word boundary. The program-to-Data

Space mapping feature, known as Program Space

Visibility (PSV), lets any instruction access Program

Space as if it were Data Space. Refer to “Data

Memory” (DS70595) in the “dsPIC33/PIC24 Family

Reference Manual” for more details on PSV and table

accesses.

On dsPIC33EPXXXGS70X/80X devices, overhead-free

circular buffers (Modulo Addressing) are supported in

both X and Y address spaces. The Modulo Addressing

removes the software boundary checking overhead for

DSP algorithms. The X AGU Circular Addressing can be

used with any of the MCU class of instructions. The

X AGU also supports Bit-Reversed Addressing to

greatly simplify input or output data re-ordering for

radix-2 FFT algorithms.

3.4

Addressing Modes

The CPU supports these addressing modes:

• Inherent (no operand)

• Relative

•Literal

• Memory Direct

• Register Direct

• Register Indirect

Each instruction is associated with a predefined

addressing mode group, depending upon its functional

requirements. As many as six addressing modes are

supported for each instruction.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXGS70X/80X family

of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “dsPIC33E Enhanced

CPU” (DS70005158) in the “dsPIC33/

PIC24 Family Reference Manual”, which

is available from the Microchip website

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

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