DSPIC33EP64GS708 datasheet(95/484 Pages) MICROCHIP

95 / 484 page

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DS70005258C-page 95

dsPIC33EPXXXGS70X/80X FAMILY

DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER

R/S-0

U-0

FORCE(1)

—

bit 15

bit 8

R/W-0

IRQSEL<7:0>

bit 7

bit 0

Legend:

S = Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

FORCE: Force DMA Transfer bit(1)

1 = Forces a single DMA transfer (Manual mode)

0 = Automatic DMA transfer initiation by DMA request

bit 14-8

Unimplemented: Read as ‘0’

bit 7-0

IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits

01000111 = CAN2 – TX data request

01000110 = CAN1 – TX data request

00110111 = CAN2 – RX data ready

00100110 = IC4 – Input Capture 4

00100101 = IC3 – Input Capture 3

00100010 = CAN1 – RX data ready

00011111 = UART2TX – UART2 transmitter

00011110 = UART2RX – UART2 receiver

00011100 = TMR5 – Timer5

00011011 = TMR4 – Timer4

00011010 = OC4 – Output Compare 4

00011001 = OC3 – Output Compare 3

00001100 = UART1TX – UART1 transmitter

00001011 = UART1RX – UART1 receiver

00001000 = TMR3 – Timer3

00000111 = TMR2 – Timer2

00000110 = OC2 – Output Compare 2

00000101 = IC2 – Input Capture 2

00000010 = OC1 – Output Compare 1

00000001 = IC1 – Input Capture 1

00000000 = INT0 – External Interrupt 0

Note 1:

The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the

forced DMA transfer is complete or the channel is disabled (CHEN = 0).

DSPIC33EP64GS708 数据表(PDF) 95 Page - Microchip Technology

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