DSPIC33EP64GS708 datasheet(63/484 Pages) MICROCHIP

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DS70005258C-page 63

dsPIC33EPXXXGS70X/80X FAMILY

5.0

FLASH PROGRAM MEMORY

The dsPIC33EPXXXGS70X/80X family devices contain

internal Program Flash Memory for storing and

executing application code. The memory is readable,

writable and erasable during normal operation over the

entire VDD range.

Flash memory can be programmed in three ways:

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

• Run-Time Self-Programming (RTSP)

ICSP allows for a dsPIC33EPXXXGS70X/80X family

device to be serially programmed while in the end

application circuit. This is done with a programming

clock and programming data (PGECx/PGEDx) line,

and three other lines for power (VDD), ground (VSS) and

Master Clear (MCLR). This allows customers to

manufacture boards with unprogrammed devices and

then program the device just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

Enhanced In-Circuit Serial Programming uses an

on-board bootloader, known as the Program Executive,

to manage the programming process. Using an SPI data

frame format, the Program Executive can erase,

program and verify program memory. For more informa-

tion on Enhanced ICSP, see the device programming

specification.

RTSP is accomplished using TBLRD (Table Read) and

TBLWT (Table Write) instructions. With RTSP, the user

application can write program memory data with a

single program memory word and erase program mem-

ory in blocks or ‘pages’ of 512 instructions (1536 bytes)

at a time.

5.1

Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the Table Read and Table

Write instructions. These instructions allow direct read

and write access to the program memory space, from

the data memory, while the device is in normal operating

mode. The 24-bit target address in the program memory

is formed using bits<7:0> of the TBLPAG register and

the Effective Address (EA) from a W register, specified

in the table instruction, as shown in Figure 5-1. The

TBLRDL and the TBLWTL instructions are used to read or

write to bits<15:0> of program memory. TBLRDL and

TBLWTL can access program memory in both Word and

Byte modes. The TBLRDH and TBLWTH instructions are

used to read or write to bits<23:16> of program memory.

TBLRDH and TBLWTH can also access program memory

in Word or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXGS70X/80X family

of devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to “Dual Partition Flash Program

Memory” (DS70005156) in the “dsPIC33/

PIC24 Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Program Counter

24 Bits

Program Counter

TBLPAG Reg

8 Bits

Working Reg EA

16 Bits

Byte

24-Bit EA

1/0

Select

Using

Table Instruction

Using

User/Configuration

Space Select

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