DSPIC33EP64GS708 datasheet(67/484 Pages) MICROCHIP

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DS70005258C-page 67

dsPIC33EPXXXGS70X/80X FAMILY

NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER

R/SO-0(1)

R/W-0(1)

R/W-0

R/C-0

R-0

R/W-0

R/C-0

WREN

WRERR

NVMSIDL(2)

SFTSWP(6)

P2ACTIV(6)

RPDF

URERR

bit 15

bit 8

U-0

R/W-0(1)

—

—NVMOP3(3,4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4)

bit 7

bit 0

Legend:

C = Clearable bit

SO = Settable Only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

WR: Write Control bit(1)

1 = Initiates a Flash Memory Program or erase operation; the operation is self-timed and the bit is

cleared by hardware once the operation is complete

0 = Program or erase operation is complete and inactive

bit 14

WREN: Write Enable bit(1)

1 = Enables Flash program/erase operations

0 = Inhibits Flash program/erase operations

bit 13

WRERR: Write Sequence Error Flag bit(1)

1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12

NVMSIDL: NVM Stop in Idle Control bit(2)

1 = Flash voltage regulator goes into Standby mode during Idle mode

0 = Flash voltage regulator is active during Idle mode

bit 11

SFTSWP: Partition Soft Swap Status bit(6)

1 = Partitions have been successfully swapped using the BOOTSWP instruction (soft swap)

0 = Awaiting successful partition swap using the BOOTSWP instruction or a device Reset will determine

the Active Partition based on the FBTSEQ register

bit 10

P2ACTIV: Partition 2 Active Status bit(6)

1 = Partition 2 Flash is mapped into the active region

0 = Partition 1 Flash is mapped into the active region

bit 9

RPDF: Row Programming Data Format bit

1 = Row data to be stored in RAM is in compressed format

0 = Row data to be stored in RAM is in uncompressed format

Note 1:

These bits can only be reset on a POR.

If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a

delay (TVREG) before Flash memory becomes operational.

All other combinations of NVMOP<3:0> are unimplemented.

Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.

Two adjacent words on a 4-word boundary are programmed during execution of this operation.

Only applicable when operating in Dual Partition mode.

The specific Boot mode depends on bits<1:0> of the programmed data:

11 = Single Partition Flash mode

10 = Dual Partition Flash mode

01 = Protected Dual Partition Flash mode

00 = Reserved

DSPIC33EP64GS708 数据表(PDF) 67 Page - Microchip Technology

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