DSPIC33EP64GS708 datasheet(71/484 Pages) MICROCHIP

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DS70005258C-page 71

dsPIC33EPXXXGS70X/80X FAMILY

6.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR: Master Clear Pin Reset

•SWR: RESET Instruction

• WDTO: Watchdog Timer Time-out Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST

signal active. On system Reset, some of the registers

associated with the CPU and peripherals are forced to

a known Reset state, and some are unaffected.

All types of device Reset set a corresponding status bit

in the RCON register to indicate the type of Reset (see

A POR clears all the bits, except for the BOR and POR

bits (RCON<1:0>) that are set. The user application

can set or clear any bit, at any time, during code

execution. The RCON bits only serve as status bits.

Setting a particular Reset status bit in software does

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

For all Resets, the default clock source is determined

by the FNOSC<2:0> bits in the FOSCSEL Configura-

tion register. The value of the FNOSCx bits is loaded

into the NOSC<2:0> (OSCCON<10:8>) bits on Reset,

which in turn, initializes the system clock.

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

Note 1: This

data

sheet

summarizes

the

features of the dsPIC33EPXXXGS70X/

80X family of devices. It is not intended to

be a comprehensive reference source. To

complement the information in this data

sheet, refer to “Reset” (DS70602) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

website (www.microchip.com)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

Refer to the specific peripheral section or

Section 4.0 “Memory Organization” of

this data sheet for register Reset states.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset is meaningful.

MCLR

VDD

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

Configuration Mismatch

Security Reset

Internal

Regulator

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