DSPIC33EP64GS708 datasheet(68/484 Pages) MICROCHIP

68 / 484 page

dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 68

 2016-2018 Microchip Technology Inc.

bit 8

URERR: Row Programming Data Underrun Error bit

1 = Indicates row programming operation has been terminated

0 = No data underrun error is detected

bit 7-4

Unimplemented: Read as ‘0’

bit 3-0

NVMOP<3:0>: NVM Operation Select bits(1,3,4)

1111 = Reserved

1110 = User memory bulk erase operation

1011 = Reserved

1010 = Reserved

1001 = Reserved

1000 = Boot memory double-word program operation in a Dual Partition Flash mode(7)

0101 = Reserved

0100 = Inactive Partition memory erase operation

0011 = Memory page erase operation

0010 = Memory row program operation

0001 = Memory double-word program operation(5)

0000 = Reserved

NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)

Note 1:

These bits can only be reset on a POR.

If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a

delay (TVREG) before Flash memory becomes operational.

All other combinations of NVMOP<3:0> are unimplemented.

Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.

Two adjacent words on a 4-word boundary are programmed during execution of this operation.

Only applicable when operating in Dual Partition mode.

The specific Boot mode depends on bits<1:0> of the programmed data:

11 = Single Partition Flash mode

10 = Dual Partition Flash mode

01 = Protected Dual Partition Flash mode

00 = Reserved

DSPIC33EP64GS708 数据表(PDF) 68 Page - Microchip Technology

DSPIC33EP64GS708 数据表(HTML) 68 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载