DSPIC33EP64GS708 datasheet(91/484 Pages) MICROCHIP

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 2016-2018 Microchip Technology Inc.

DS70005258C-page 91

dsPIC33EPXXXGS70X/80X FAMILY

8.0

DIRECT MEMORY ACCESS

(DMA)

The DMA Controller transfers data between Peripheral

Data registers and Data Space SRAM.

In addition, DMA can access the entire data memory

space. The data memory bus arbiter is utilized when

either the CPU or DMA attempts to access SRAM,

resulting in potential DMA or CPU Stalls.

The DMA Controller supports four independent

channels. Each channel can be configured for transfers

to or from selected peripherals. The peripherals

supported by the DMA Controller include:

•CAN

•UART

• Input Capture

• Output Compare

•Timers

Refer to Table 8-1 for a complete list of supported

peripherals.

FIGURE 8-1:

PERIPHERAL TO DMA CONTROLLER

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXGS70X/80X family

of devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data

sheet, refer to “Direct Memory Access

(DMA)” (DS70348) in the “dsPIC33/

PIC24 Family Reference Manual”, which

is available from the Microchip website

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

DMA

PERIPHERAL

Data Memory

SRAM

(see Figure 4-10)

Arbiter

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