DSPIC33EP64GS708 datasheet(17/484 Pages) MICROCHIP

17 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 17

dsPIC33EPXXXGS70X/80X FAMILY

2.0

GUIDELINES FOR GETTING

STARTED WITH 16-BIT DIGITAL

SIGNAL CONTROLLERS

2.1

Basic Connection Requirements

Getting started with the dsPIC33EPXXXGS70X/80X

family requires attention to a minimal set of device pin

connections before proceeding with development. The

following is a list of pin names which must always be

connected:

•All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

•All AVDD and AVSS pins

regardless if ADC module is not used (see

Section 2.2 “Decoupling Capacitors”)

•VCAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (VCAP)”)

•MCLR pin

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins

used for In-Circuit Serial Programming™ (ICSP™)

and debugging purposes (see Section 2.5 “ICSP

Pins”)

• OSC1 and OSC2 pins

when external oscillator source is used (see

Section 2.6 “External Oscillator Pins”)

2.2

Decoupling Capacitors

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

Consider the following criteria when using decoupling

capacitors:

• Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should

be a low-ESR and have resonance frequency in

the range of 20 MHz and higher. It is

recommended to use ceramic capacitors.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

• Handling high-frequency noise: If the board is

experiencing high-frequency noise, above tens

of MHz, add a second ceramic-type capacitor in

parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Place this

second capacitor next to the primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB track

inductance.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXGS70X/80X family

of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section of

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

DSPIC33EP64GS708 数据表(PDF) 17 Page - Microchip Technology

DSPIC33EP64GS708 数据表(HTML) 17 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载