DSPIC33EP64GS708 datasheet(75/484 Pages) MICROCHIP

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DS70005258C-page 75

dsPIC33EPXXXGS70X/80X FAMILY

7.0

INTERRUPT CONTROLLER

The dsPIC33EPXXXGS70X/80X family interrupt

controller reduces the numerous peripheral interrupt

request signals to a single interrupt request signal to

the dsPIC33EPXXXGS70X/80X family CPU.

The interrupt controller has the following features:

• Six Processor Exceptions and Software Traps

• Seven User-Selectable Priority Levels

• Interrupt Vector Table (IVT) with a Unique Vector

for each Interrupt or Exception Source

• Fixed Priority within a Specified User Priority

Level

• Fixed Interrupt Entry and Return Latencies

• Alternate Interrupt Vector Table (AIVT) for Debug

Support

7.1

Interrupt Vector Table

The dsPIC33EPXXXGS70X/80X family Interrupt Vector

Table (IVT), shown in Figure 7-1, resides in program

memory, starting at location, 000004h. The IVT con-

tains six non-maskable trap vectors and up to

246 sources of interrupts. In general, each interrupt

source has its own vector. Each interrupt vector

contains a 24-bit wide address. The value programmed

into each interrupt vector location is the starting

address of the associated Interrupt Service Routine

(ISR).

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with Vector 0 takes priority over interrupts at any other

vector address.

7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

The Alternate Interrupt Vector Table (AIVT), shown in

Figure 7-2, is available only when the Boot Segment is

defined and the AIVT has been enabled. To enable the

Alternate Interrupt Vector Table, the Configuration bit,

AIVTDIS in the FSEC register, must be programmed

and the AIVTEN bit must be set (INTCON2<8> = 1).

When the AIVT is enabled, all interrupt and exception

processes use the alternate vectors instead of the

default vectors. The AIVT begins at the start of the last

page of the Boot Segment, defined by BSLIM<12:0>.

The second half of the page is no longer usable space.

The Boot Segment must be at least two pages to

enable the AIVT.

The AIVT supports debugging by providing a means to

switch between an application and a support environ-

ment without requiring the interrupt vectors to be

reprogrammed. This feature also enables switching

between applications for evaluation of different

software algorithms at run time.

7.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The dsPIC33EPXXXGS70X/80X family devices clear

their registers in response to a Reset, which forces the

PC to zero. The device then begins program execution

at location, 0x000000. A GOTO instruction at the Reset

address can redirect program execution to the

appropriate start-up routine.

Note 1: This

data

sheet

summarizes

the

features of the dsPIC33EPXXXGS70X/

80X family of devices. It is not intended to

be a comprehensive reference source. To

complement the information in this data

sheet, refer to “Interrupts” (DS70000600)

in the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

Although the Boot Segment must be

enabled in order to enable the AIVT,

application code does not need to be

present inside of the Boot Segment. The

AIVT (and IVT) will inherit the Boot

Segment code protection.

Note:

Any unimplemented or unused vector

locations

the

IVT

should

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

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