DSPIC33EP64GS708 datasheet(38/484 Pages) MICROCHIP

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dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 38

 2016-2018 Microchip Technology Inc.

4.2.1

PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 4-5).

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two, during code execution. This

arrangement provides compatibility with data memory

space addressing and makes data in the program

memory space accessible.

4.2.2

INTERRUPT AND TRAP VECTORS

All dsPIC33EPXXXGS70X/80X family devices reserve

the addresses between 0x000000 and 0x000200 for

hard-coded program execution vectors. A hardware

Reset vector is provided to redirect code execution

from the default value of the PC on device Reset to the

actual start of code. A GOTO instruction is programmed

by the user application at address, 0x000000, of Flash

memory, with the actual address for the start of code at

address, 0x000002, of Flash memory.

A more detailed discussion of the Interrupt Vector

Tables (IVTs) is provided in Section 7.1 “Interrupt

Vector Table”.

FIGURE 4-5:

PROGRAM MEMORY ORGANIZATION

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001

0x000003

0x000005

0x000007

msw

Address

(lsw Address)

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