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DSPIC33EP64GS708 数据表(PDF) 15 Page - Microchip Technology |
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DSPIC33EP64GS708 数据表(HTML) 15 Page - Microchip Technology |
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15 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 15 dsPIC33EPXXXGS70X/80X FAMILY U2CTS U2RTS U2RX U2TX BCLK2 I O I O O ST — ST — ST Yes Yes Yes Yes Yes UART2 Clear-to-Send. UART2 Ready-to-Send. UART2 receive. UART2 transmit. UART2 IrDA baud clock output. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCK2 SDI2 SDO2 SS2 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. SCK3 SDI3 SDO3 SS3 I/O I O I/O ST ST — ST Yes(3) Yes Yes Yes Synchronous serial clock input/output for SPI3. SPI3 data in. SPI3 data out. SPI3 slave synchronization or frame pulse I/O. SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. SCL2 SDA2 ASCL2 ASDA2 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. Alternate synchronous serial clock input/output for I2C2. Alternate synchronous serial data input/output for I2C2. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. FLT1-FLT8 FLT9-FLT12 FLT17-FLT22 FLT31 PWM1L-PWM3L PWM1H-PWM3H PWM4L-PWM8L(2) PWM4H-PWM8H(2) SYNCI1, SYNCI2 SYNCO1, SYNCO2 I I I I O O O O I O ST ST ST ST — — — — ST — Yes No No No No No Yes Yes Yes Yes PWM Fault Inputs 1 through 8. PWM Fault Inputs 9 through 12. PWM Fault Inputs 17 through 22. PWM Fault Input 31 (Class B Fault). PWM Low Outputs 1 through 3. PWM High Outputs 1 through 3. PWM Low Outputs 4 through 8. PWM High Outputs 4 through 8. PWM Synchronization Inputs 1 and 2. PWM Synchronization Outputs 1 and 2. TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name(1) Pin Type Buffer Type PPS Description Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select 1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability. 2: PWM4H/L through PWM8H/L are fixed on dsPIC33EPXXXGS708/808 devices. PWM4H/L through PWM6H/L are fixed on dsPIC33EPXXXGS706/806 devices. 3: The SCK3 pin is fixed on dsPIC33EPXXXGS706/806 and dsPIC33EPXXXGS708/808 devices. 4: PPS is available on dsPIC33EPXXXGS702 devices only. |
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