DSPIC33EP64GS708 datasheet(127/484 Pages) MICROCHIP

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 2016-2018 Microchip Technology Inc.

DS70005258C-page 127

dsPIC33EPXXXGS70X/80X FAMILY

11.0 I/O PORTS

Many of the device pins are shared among the periph-

erals and the Parallel I/O ports. All I/O input ports feature

Schmitt Trigger inputs for improved noise immunity.

11.1

Parallel I/O (PIO) Ports

Generally, a Parallel I/O port that shares a pin with a

peripheral is subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 illus-

trates how ports are shared with other peripherals and

the associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as a

general purpose output pin is disabled. The I/O pin can

be read, but the output driver for the parallel port bit is

disabled. If a peripheral is enabled, but the peripheral is

not actively driving a pin, that pin can be driven by a port.

All port pins have eight registers directly associated with

their operation as digital I/Os. The Data Direction register

(TRISx) determines whether the pin is an input or an out-

put. If the data direction bit is a ‘1’, then the pin is an input.

All port pins are defined as inputs after a Reset. Reads

from the latch (LATx), read the latch. Writes to the latch,

write the latch. Reads from the port (PORTx), read the

port pins, while writes to the port pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device are disabled.

This means the corresponding LATx and TRISx

registers, and the port pin are read as zeros. Table 11-1

through Table 11-5 show ANSELx bits’ availability for

device variants.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXXGS70X/80X family

of devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to “I/O Ports” (DS70000598) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

WR LATx +

TRISx Latch

I/O Pin

WR PORTx

Data Bus

Data Latch

Read PORTx

Read TRISx

WR TRISx

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LATx

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