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DSPIC33EP64GS708 数据表(PDF) 149 Page - Microchip Technology |
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DSPIC33EP64GS708 数据表(HTML) 149 Page - Microchip Technology |
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149 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 149 dsPIC33EPXXXGS70X/80X FAMILY REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2CTSR7 U2CTSR6 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2RXR7 U2RXR6 U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 U2CTSR<7:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits See Table 11-11 which contains a list of remappable inputs for the index value. bit 7-0 U2RXR<7:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits See Table 11-11 which contains a list of remappable inputs for the index value. REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SCK1INR7 SCK1INR6 SCK1INR5 SCK1INR4 SCK1INR3 SCK1INR2 SCK1INR1 SCK1INR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDI1R7 SDI1R6 SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 SCK1INR<7:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits See Table 11-11 which contains a list of remappable inputs for the index value. bit 7-0 SDI1R<7:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits See Table 11-11 which contains a list of remappable inputs for the index value. |
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