DSPIC33EP64GS708 datasheet(171/484 Pages) MICROCHIP

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DS70005258C-page 171

dsPIC33EPXXXGS70X/80X FAMILY

12.0 TIMER1

The Timer1 module is a 16-bit timer that can operate as

a free-running interval timer/counter.

The Timer1 module has the following unique features

over other timers:

• Can be Operated in Asynchronous Counter mode

from an External Clock Source

• The External Clock Input (T1CK) can Optionally be

Synchronized to the Internal Device Clock and the

Clock Synchronization is Performed after the

prescaler

A block diagram of Timer1 is shown in Figure 12-1.

The Timer1 module can operate in one of the following

modes:

• Timer mode

• Gated Timer mode

• Synchronous Counter mode

• Asynchronous Counter mode

In Timer and Gated Timer modes, the input clock is

derived from the internal instruction cycle clock (FCY).

In Synchronous and Asynchronous Counter modes,

the input clock is derived from the external clock input

at the T1CK pin.

The Timer modes are determined by the following bits:

• Timer1 Clock Source Select bit (TCS): T1CON<1>

• Timer1 External Clock Input Synchronization Select

bit (TSYNC): T1CON<2>

• Timer1 Gated Time Accumulation Enable bit

(TGATE): T1CON<6>

Timer control bit settings for different operating modes

are provided in Table 12-1.

TABLE 12-1:

TIMER1 MODE SETTINGS

FIGURE 12-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note 1: This

data

sheet

summarizes

the

features of the dsPIC33EPXXXGS70X/

80X family of devices. It is not intended to

be a comprehensive reference source. To

complement the information in this data

sheet, refer to “Timers” (DS70362) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Mode

TCS

TGATE

TSYNC

Timer

Gated Timer

Synchronous

Counter

Asynchronous

Counter

TGATE

TCS

PR1

TGATE

Set T1IF Flag

TSYNC

Sync

Equal

Reset

T1CK

Prescaler

(/n)

TCKPS<1:0>

Gate

Sync

FP(1)

Falling Edge

Detect

TCKPS<1:0>

Note 1:

FP is the peripheral clock.

Latch

Data

CLK

T1CLK

ADC Trigger

TMR1

Comparator

Prescaler

(/n)

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