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PCF8564A 数据表(PDF) 15 Page - NXP Semiconductors

部件名 PCF8564A
功能描述  Nano-power highly accurate RTC with integrated quartz crystal for automotive applications
PDF  86 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8564A 数据表(HTML) 15 Page - NXP Semiconductors

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NXP Semiconductors
PCA2131
Nano-power highly accurate RTC with integrated quartz crystal for automotive applications
7.3.1.1 Temperature measurement
The PCA2131 has a temperature sensor circuit used to perform temperature
compensation of the clock input to the RTC. The temperature is measured immediately
after power-on and then periodically with a period set by the temperature conversion
rate TCR[1:0] in the register CLKOUT_ctl. During the first approximately 60 s after start-
up the compensation will be inactive, after this period the temperature compensation is
active.
TCR[1:0]
Temperature measurement period
00
[1] 32 min
01
16 min
10
8 min
11
4 min
Table 17. Temperature measurement period
[1]
Default value.
7.3.2 OTP refresh
Each IC is calibrated during production and testing of the device. The calibration
parameters are stored on EPROM cells called One Time Programmable (OTP) cells. It is
recommended to process an OTP refresh once after the power is up and the oscillator is
operating stable. The OTP refresh takes less than 100 ms to complete.
To perform an OTP refresh, bit OTPR has to be cleared (set to logic 0) and then set to
logic 1 again.
When read OTPR bit, its state is:
"0" until the OTP read state machine completes copying of the eFuse data into the
shadow registers. This could be due to a POR event or to writing a 0 > 1 to the OTPR
register bit.
"1" when the OTP read state machine completes copying to the shadow registers from
the eFuse instances. During normal operation OTPR must be kept at 1 to prevent higher
power usage.
The OTP logic is not reset nor affected by the Software Reset. The OTPR functionality is
only reset by the initial digital POR.
During OTP refresh, VDD has to be above 1.8 V, the rising speed to 1.8 V needs to be
faster than 2 V/100 ms. After OTP refresh has finished, PCA2131 can operate with VDD
as low as 1.2 V.
7.3.3 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down
to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump
input, or for calibrating the oscillator at 25 °C to determine aging offset. The CLKOUT
output is not temperature compensated to prevent jitter due to digital compensation
method.
CLKOUT is a push-pull output and is enabled at power-on. When disabled, the output is
high-impedance.
PCA2131
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.0 — 26 July 2021
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