PCF8564A datasheet(56/86 Pages) NXP

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NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgment on the I2C-bus is illustrated in Figure 32.

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Figure 32. Acknowledgment on the I2C-bus

7.16.2.5 I2C-bus protocol

After a start condition, a valid hardware address has to be sent to a PCA2131 device.

The appropriate I2C-bus slave address is 1010 011. The entire I2C-bus slave address

byte is shown in Table 87.

Slave address

Bit

MSB

LSB

R/W

Table 87. I2C slave address byte

The R/W bit defines the direction of the following single or multiple byte data transfer

(read is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and

the acknowledge (A) refer to the I2C-bus specification [3] and the characteristics table

(Table 92). In the write mode, a data transfer is terminated by sending a STOP condition.

aaa-041582

0 to n (data bytes

plus ACK)

slave address

write bit

00h to 36h

acknowledge

from PCA2131

acknowledge

from PCA2131

acknowledge

from PCA2131

STOP

START

Figure 33. Bus protocol, writing to registers

PCA2131

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Product data sheet

Rev. 1.0 — 26 July 2021

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