PCF8564A datasheet(53/86 Pages) NXP

53 / 86 page

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

Symbol

Function

Description

SDA/CE

chip enable input;

active LOW

[1] when HIGH, the interface is reset;

input may be higher than VDD

SCL

serial clock input

when SDA/CE is HIGH, input may float;

input may be higher than VDD

SDI

serial data input

when SDA/CE is HIGH, input may float;

input may be higher than VDD;

input data is sampled on the rising edge of

SCL

SDO

serial data output

push-pull output;

drives from VSS to Voper(int) (VBBS);

output data is changed on the falling edge of

SCL

Table 85. Serial interface

[1]

The chip enable must not be wired permanently LOW.

7.16.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

whole byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes are either data to be written or

data to be read (see Figure 26).

SDO

aaa-041579

SDA/CE

DATA

SDI

COMMAND

DATA

Figure 26. Data transfer overview

The command byte defines the address of the first register to be accessed and the read/

write mode. The address counter will auto increment after every access and will reset to

zero after the last valid register is accessed. The R/W bit defines if the following bytes are

read or write information.

Bit

Symbol

Value

Description

data read or write selection

write data

R/W

read data

6 to 0

00h to 36h

Table 86. Command byte definition

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

53 / 86

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