PCF8564A datasheet(50/86 Pages) NXP

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NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

7.14 External clock test mode

A test mode is available which allows on-board testing. In this mode, it is possible to set

up test conditions and control the operation of the RTC.

The test mode is entered by setting bits COF[2:0] logic 111 (register CLKOUT_ctl) and bit

EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test

mode replaces the internal clock signal (8192 Hz) with the signal applied to pin CLKOUT.

Every 8192 positive edges applied to pin CLKOUT generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

minimum period of 1 000 ns. The internal clock, now sourced from CLKOUT, is divided

down by a divider chain called prescaler. The prescaler can be set into a known state by

using bit STOP and CPR. When bit STOP and CPR are logic 1, the prescaler is reset to

0. STOP and CPR must be cleared before the prescaler can operate again.

From a stop condition, the first 1 second increment will take place after 8192 positive

edges on pin CLKOUT. Thereafter, every 8192 positive edges cause a 1 second

increment. In 100 Hz mode, the first 100th of a second increment will take place after

80 pulses on pin CLKOUT, and the first 1 second increment will take place after 8176

pulses on pin CLKOUT. Thereafter, every 8192 pulses cause a 1 second increment. The

100 Hz clock is generated from a dithered state machine which runs on the 256 Hz clock,

so the number of pulses for each subsequent 100ths change is not constant. After the

first 1 second increment the 25-bit dither pattern proceeds as follows from left to right:

1101010101101010110101010

Where 1 == 96 CLKOUT pulses, and 0 == 64 CLKOUT pulses. This pattern repeats

4 times every second.In the first second, after 80 clock pulses trigger the first

100th,the left pattern is 101010101101010110101010, 1101010101101010110101010,

1101010101101010110101010, 1101010101101010110101010, which means 96 pulses

for 100ths == 2, then 64 pulses for 100ths == 3, 96 for 100ths == 4, and so on.

Remark: Entry into test mode is not synchronized to the internal 8192 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operating example:

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111).

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

6. Clear STOP (register Control_1, STOP is logic 0).

7. Apply 8192 clock pulses to CLKOUT.

8. Read time registers to see the first change.

9. Apply 8192 clock pulses to CLKOUT.

10.Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Operating example (100 Hz mode):

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111.

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

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