PCF8564A datasheet(23/86 Pages) NXP

23 / 86 page

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

001aaj409

(1)

Vth(sw)bat

(= 2.5 V)

VSS

VBAT

Vlow

(= 1.2 V)

VDD

Voper(int)

VDD

VBAT

VSS

(2)

OSF

battery discharge

VDD

1. Theoretical state of the signals since there is no power.

2. The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a

reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity

of the clock information is not guaranteed. The OSF flag is cleared by command.

Figure 8. Power failure event due to battery discharge: reset occurs

7.7 Power-On Reset function

The PCA2131 has a Power-On Reset (POR) and a Power-On Reset Override (PORO)

function implemented.

7.7.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is considered to be

stopped during the time between power-on and stable crystal resonance (see Figure 9).

This time may be in the range of 200 ms to 2 s depending on temperature and supply

voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic

1).

The OTP refresh (see Section 7.3.2) should ideally be executed as the first instruction

after start-up and also after a reset due to an oscillator stop.

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

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