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PCF8564A 数据表(PDF) 47 Page - NXP Semiconductors |
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PCF8564A 数据表(HTML) 47 Page - NXP Semiconductors |
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47 / 86 page ![]() NXP Semiconductors PCA2131 Nano-power highly accurate RTC with integrated quartz crystal for automotive applications aaa-041572 58 seconds counter minutes counter INTA/B when SI enable MSF when SI enable INTA/B when only MI enabled MSF when only MI enabled 59 59 11 00 00 01 12 In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt. Figure 19. INTA/B example for SI and MI when TI_TP is logic 0 The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 1⁄64 seconds in duration. 7.13.2 INTA/B pulse shortening If the MSF flag (register Control_2) is cleared before the end of the INTA/B pulse, then the INTA/B pulse is shortened. This allows the source of a system interrupt to be cleared immediately when it is serviced, that is, the system does not have to wait for the completion of the pulse before continuing; see Figure 20. Instructions for clearing the bit MSF can be found in Section 7.11.5. aaa-041573 58 seconds counter MSF INTA/B SCL instruction 59 CLEAR INSTRUCTION 8th clock (1) 1. Indicates normal duration of INTA/B pulse. The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is, when TI_TP is logic 0, where the INTA/B pulse may be shortened by setting both bits MI and SI logic 0. Figure 20. Example of shortening the INTA/B pulse by clearing the MSF flag 7.13.3 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD bit (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2) if not masked. No pulse generation is possible for watchdog timer interrupts. PCA2131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1.0 — 26 July 2021 47 / 86 |
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