数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

PCF8564A 数据表(PDF) 47 Page - NXP Semiconductors

部件名 PCF8564A
功能描述  Nano-power highly accurate RTC with integrated quartz crystal for automotive applications
PDF  86 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8564A 数据表(HTML) 47 Page - NXP Semiconductors

Back Button PCF8564A Datasheet HTML 43Page - NXP Semiconductors PCF8564A Datasheet HTML 44Page - NXP Semiconductors PCF8564A Datasheet HTML 45Page - NXP Semiconductors PCF8564A Datasheet HTML 46Page - NXP Semiconductors PCF8564A Datasheet HTML 47Page - NXP Semiconductors PCF8564A Datasheet HTML 48Page - NXP Semiconductors PCF8564A Datasheet HTML 49Page - NXP Semiconductors PCF8564A Datasheet HTML 50Page - NXP Semiconductors PCF8564A Datasheet HTML 51Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 47 / 86 page
background image
NXP Semiconductors
PCA2131
Nano-power highly accurate RTC with integrated quartz crystal for automotive applications
aaa-041572
58
seconds counter
minutes counter
INTA/B when SI enable
MSF when SI enable
INTA/B when only MI enabled
MSF when only MI enabled
59
59
11
00
00 01
12
In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.
Figure 19. INTA/B example for SI and MI when TI_TP is logic 0
The pulse generator for the minute/second interrupt operates from an internal 64 Hz
clock and generates a pulse of 164 seconds in duration.
7.13.2 INTA/B pulse shortening
If the MSF flag (register Control_2) is cleared before the end of the INTA/B pulse,
then the INTA/B pulse is shortened. This allows the source of a system interrupt to be
cleared immediately when it is serviced, that is, the system does not have to wait for the
completion of the pulse before continuing; see Figure 20. Instructions for clearing the bit
MSF can be found in Section 7.11.5.
aaa-041573
58
seconds counter
MSF
INTA/B
SCL
instruction
59
CLEAR INSTRUCTION
8th clock
(1)
1. Indicates normal duration of INTA/B pulse.
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is,
when TI_TP is logic 0, where the INTA/B pulse may be shortened by setting both bits MI and SI
logic 0.
Figure 20. Example of shortening the INTA/B pulse by clearing the MSF flag
7.13.3 Watchdog timer interrupts
The generation of interrupts from the watchdog timer is controlled using the WD_CD bit
(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows
the status of the watchdog timer flag WDTF (register Control_2) if not masked. No pulse
generation is possible for watchdog timer interrupts.
PCA2131
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.0 — 26 July 2021
47 / 86



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com