PCF8564A datasheet(67/86 Pages) NXP

67 / 86 page

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of VSS to VDD (see Figure 41).

Standard mode

Fast-mode (Fm)

Symbol

Parameter

Min

Max

Min

Max

Unit

tSU;STO

set-up time for STOP condition

4.0

0.6

µs

tHD;STA

hold time (repeated) START

condition

4.0

0.6

µs

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

µs

rise time of both SDA and SCL

signals

[2][3][4] -

1 000

20 + 0.1Cb

300

fall time of both SDA and SCL

signals

[2][3][4] -

300

20 + 0.1Cb

300

tVD;ACK

data valid acknowledge time

[5] -

3.45

0.9

µs

tVD;DAT

data valid time

[6] -

3.45

0.9

tSP

pulse width of spikes that must

be suppressed by the input filter

[7] -

Table 92. I2C-bus characteristics...continued

[1]

The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a

minimum of 25 ms. The bus time-out feature must be disabled for DC operation.

[2]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the

undefined region of the falling edge of SCL.

[3]

Cb is the total capacitance of one bus line in pF.

[4]

The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection

resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the maximum tf.

[5]

tVD;ACK is the time of the acknowledgment signal from SCL LOW to SDA (out) LOW.

[6]

tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.

[7]

Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

PROTOCOL

SCL

SDA

mbd820

BIT 0

LSB

(R/W)

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

tSU;STA

tHD;STA

tSU;DAT

tHD;DAT

tVD;DAT

tSU;STO

tLOW

tHIGH

1 / fSCL

tBUF

Figure 41. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

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