PCF8564A datasheet(83/86 Pages) NXP

83 / 86 page

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

Tab. 65. Timestp_ctl1/2/3/4 - timestamp control

description ....................................................... 41

Tab. 66. Sec_timestp1/2/3/4 - second timestamp

allocation ......................................................... 42

Tab. 67. Sec_timestp1/2/3/4 - second timestamp

description ....................................................... 42

Tab. 68. Min_timestp1/2/3/4 - minute timestamp

allocation ......................................................... 42

Tab. 69. Min_timestp1/2/3/4 - minute timestamp

description ....................................................... 42

Tab. 70. Hour_timestp1/2/3/4 - hour timestamp

allocation ......................................................... 42

Tab. 71. Hour_timestp1/2/3/4 - hour timestamp

description ....................................................... 43

Tab. 72. Day_timestp1/2/3/4 - day timestamp

allocation ......................................................... 43

Tab. 73. Day_timestp1/2/3/4 - day timestamp

description ....................................................... 43

Tab. 74. Mon_timestp1/2/3/4 - month timestamp

allocation ......................................................... 43

Tab. 75. Mon_timestp1/2/3/4 - month timestamp

description ....................................................... 44

Tab. 76. Year_timestp1/2/3/4 - year timestamp

allocation ......................................................... 44

Tab. 77. Year_timestp1/2/3/4 - year timestamp

description ....................................................... 44

Tab. 78. Battery switch-over and timestamp ................. 44

Tab. 79. Effect of bits MI and SI on pin INTA/B and

bit MSF ............................................................46

Tab. 80. INT_A/B_MASK1 - interrupt mask 1

Tab. 81. INT_A/B_MASK1 - interrupt mask 1

Tab. 82. INT_A/B_MASK2 - interrupt mask 2

Tab. 83. INT_A/B_MASK2 - interrupt mask 2

Tab. 84. Interface selection input pin IFS ......................52

Tab. 85. Serial interface ................................................ 53

Tab. 86. Command byte definition ................................ 53

Tab. 87. I2C slave address byte ................................... 56

Tab. 88. Limiting values ................................................ 58

Tab. 89. Static characteristics ....................................... 59

Tab. 90. Frequency characteristics ............................... 63

Tab. 91. SPI-bus characteristics ....................................65

Tab. 92. I2C-bus characteristics ....................................66

Tab. 93. Selection of Real-Time Clocks ........................ 76

Tab. 94. Abbreviations ...................................................78

Tab. 95. Revision history ...............................................79

Figures

Fig. 1.

Block diagram of PCA2131 ...............................3

Fig. 2.

Pin configuration for PCA2131 (transparent

top view) ............................................................4

Fig. 3.

Handling address registers ............................... 5

Fig. 4.

Battery switch-over behavior in standard

mode with bit BIE set logic 1 (enabled) ........... 19

Fig. 5.

Battery switch-over behavior in direct

switching mode with bit BIE set logic 1

(enabled) ......................................................... 20

Fig. 6.

Battery switch-over circuit, simplified block

diagram ............................................................20

Fig. 7.

Battery low detection behavior with bit BLIE

set logic 1 (enabled) ....................................... 21

Fig. 8.

Power failure event due to battery

discharge: reset occurs ...................................23

Fig. 9.

Dependency between POR and oscillator .......24

Fig. 10.

Power-On Reset (POR) system ...................... 24

Fig. 11.

Power-On Reset Override (PORO)

sequence, valid for both I2C-bus and SPI-

bus ...................................................................25

Fig. 12.

Software reset command ................................ 26

Fig. 13.

Data flow for the time function ........................ 32

Fig. 14.

Alarm function block diagram ..........................33

Fig. 15.

Alarm flag timing diagram ............................... 36

Fig. 16.

WD_CD set logic 1: watchdog activates an

interrupt when timed out ................................. 39

Fig. 17.

Interrupt block diagram ................................... 45

Fig. 18.

INTA/B example for SI and MI when TI_TP

is logic 1 ..........................................................46

Fig. 19.

INTA/B example for SI and MI when TI_TP

is logic 0 ..........................................................47

Fig. 20.

Example of shortening the INTA/B pulse by

clearing the MSF flag ......................................47

Fig. 21.

AF timing diagram ...........................................48

Fig. 22.

CPR and STOP bit functional diagram ............51

Fig. 23.

STOP release timing .......................................51

Fig. 24.

Interface selection ........................................... 52

Fig. 25.

SDI, SDO configurations ................................. 52

Fig. 26.

Data transfer overview .................................... 53

Fig. 27.

SPI-bus write example .................................... 54

Fig. 28.

SPI-bus read example .....................................54

Fig. 29.

Bit transfer .......................................................55

Fig. 30.

Definition of START and STOP conditions ...... 55

Fig. 31.

System configuration .......................................55

Fig. 32.

Acknowledgment on the I2C-bus .................... 56

Fig. 33.

Bus protocol, writing to registers ..................... 56

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

83 / 86

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