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PCF8564A 数据表(PDF) 61 Page - NXP Semiconductors |
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PCF8564A 数据表(HTML) 61 Page - NXP Semiconductors |
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61 / 86 page ![]() NXP Semiconductors PCA2131 Nano-power highly accurate RTC with integrated quartz crystal for automotive applications VDD = 1.2 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max 85 °C Max 105 °C Unit VIH HIGH-level input voltage 0.7VDD - - - V VI = VDD or VSS - 0 - - µA ILI input leakage current post ESD event -1 - - +1 µA Ci input capacitance [9] - - - 7 pF Outputs on pins INTA/B, referring to external pull-up -0.5 - - 5.5 V VO output voltage on pin BBS [10] 1.2 - - 5.5 V VOH HIGH output voltage on pin SDO, CLKOUT at 1 mA source current 0.8VDD - - VDD V on pins CLKOUT, INTA/ B and SDO at 1 mA sink current VSS - - 0.2VDD V on pin SDA, VDD > 2.0 V, 3 mA sink current - - - 0.4 V VOL LOW output voltage on pin SDA, VDD < 2.0 V, 2 mA sink current - - - 0.2VDD V output sink current; VOL = 0.4 V on pin SDA/CE [11] 3 - - - mA IOL LOW-level output current on all other outputs 1.0 - - - mA IOH HIGH-level output current output source current; on pin SDO, CLKOUT; VOH = 0.8 * VDD 1.0 - - - mA VO = VDD or VSS - 0 - - µA ILO output leakage current post ESD event -1 - - +1 µA Table 89. Static characteristics...continued [1] For reliable oscillator start-up and OTP refresh at power-on: VDD needs to be above 1.8 V. [2] MAX IDD and IBAT determined by characterization. [3] Timer source clock = 1⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS. [4] Production tested IDDparameter. [5] Any load in the application driven by CLKOUT adds to this value, e.g. 10 pF, Vdd = 3v3 will add 32768 Hz * 10 pF * 3.3 V = 1.1 µA. [6] Any load in the application driven by CLKOUT adds to this value, e.g. 10 pF, Vdd = 3v3 will add 32768 Hz * 10 pF * 3.3 V = 1.1 µA. [7] When the device is supplied by the VBAT pin instead of the VDD pin, VDD = 0 V. The device can only start up from VDD. [8] The I2C-bus and SPI-bus interfaces of PCA2131 are 5 V tolerant. [9] Tested on sample basis. [10] Pin BBS is internally connected to either VDD or VBAT, see section Section 7.5.3. [11] For further information, see Figure 36. PCA2131 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1.0 — 26 July 2021 61 / 86 |
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