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ADIN1110BCPZ-R7 数据表(PDF) 29 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 29 Page - Analog Devices |
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29 / 104 page  Data Sheet ADIN1110 MAC SPI analog.com Rev. 0 | 29 of 104 Table 22. Control Write Transaction with CRC MSB LSB D102 D101 D101 D100 to D89 D88 to D80 D79 to D48 D47 to D40 D39 to D8 D7 to D0 SDI 1 0 R/W ADDR[12:0] CRC[7:0] DATA0[31:0] CRC[7:0] DATA1[31:0] CRC[7:0] Table 23. Control Read Transaction with CRC MSB LSB D110 D109 D108 D107 to D96 D95 to D88 D87 to D80 D79 to D48 D47 to D40 D39 to D8 D7 to D0 SDI 1 0 R/W ADDR[12:0] CRC[7:0] TA[7:0] 0 0 0 0 SDO DATA0[31:0] CRC[7:0] DATA1[31:0] CRC[7:0] Table 24. Data Write Transaction with CRC MSB LSB D86 D85 D84 D83 to D71 D71 to D64 D63 to D32 D31 to D0 SDI 1 0 R/W ADDR[12:0] CRC[7:0] DATA0[31:0] DATA1[31:0] Table 25. Data Read Transaction with CRC MSB LSB D94 D93 D92 D91 to D80 D79 to D72 D71 to D64 D63 to D32 D31 to 0 SDI 1 0 R/W ADDR[12:0] CRC[7:0] TA[7:0] 0 0 SDO DATA0[31:0] DATA1[31:0] The generic SPI protocol is half duplex. Therefore, it is not possible to write frame data into the MAC_TX register and read from the MAC_RX register at the same time. Because of this, the SPI SCLK frequency must be 25 MHz to achieve full duplex transmissions on Ethernet at 10 Mbps. MAC Frame: Transmit and Receive The 2-byte frame header shown in Table 26 is appended to all transmitted and received frames. This always precedes the frame data (see Figure 20). Time Stamp Capture On receive, if TIME_STAMP_PRESET is asserted, an additional 4-byte or 8-byte time stamp is provided after the 2-byte header in Table 26 and before the data frame. This time stamp can then be stored or discarded by software when reading the receive FIFO. On transmit, if EGRESS_CAPTURE is set other than 00, the ADIN1110 captures the time stamp of the transmitted frame into the respective TTSCxH and TTSCxL registers. To capture time stamps, enable the counter by setting TS_EN (TS_CFG register) to 1 and setting FTSE (CONFIG0 register) to 1. Transmit Frame over SPI The following sequence must be followed when using the generic SPI protocol in store and forward mode: 1. The device defaults to operating in store and forward mode. 2. Verify that there is space for the frame by reading the transmit FIFO space register. The MAC internally appends a 2-byte size field to the frame in the FIFO, so ensure that there is sufficient space for the Ethernet frame plus 2-byte header plus 2-byte size field. 3. Write the size of the frame in bytes including the 2-byte header to the MAC transmit frame size register. If the host has append- ed a frame check sequence (FCS) to the frame, this is also included in the size. 4. Write the frame data including the 2-byte frame header to the transmit FIFO using MAC transmit register. The first byte for transmission is written to TXD, Bits[31:24]. The full frame can be written in a single burst or split up into multiple smaller burst writes. The burst write data must always be in multiples of 4 bytes, that is, the last word (4 bytes) can contain between 1 byte and 4 bytes of valid data. 5. When the end of frame (EOF) byte of a frame is read from the transmit FIFO, the bit transmit ready asserts, and an interrupt triggers if the TX_RDY_MASK is set. |
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