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ADIN1110BCPZ-R7 数据表(PDF) 61 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 61 Page - Analog Devices |
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61 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 61 of 104 Table 85. Bit Descriptions for P1_RX Bits Bit Name Description Reset Access [31:0] P1_RDR Receive Data Register. This field is only used with the generic SPI protocol. Reading this register returns the four bytes at the top of the receive FIFO and pops these four bytes from the FIFO. The upper 8 bits contain the first byte, the next 8 bits contain the second byte, and so on. When a complete frame is read out, no further data is returned from the P1 Rx FIFOs until the P1_RX_FRM_SIZE register is read first. Only used with the generic SPI protocol. 0x0 R P1 Rx Frame Count Register Address: 0xA0, Reset: 0x00000000, Name: P1_RX_FRM_CNT Table 86. Bit Descriptions for P1_RX_FRM_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_FRM_CNT Rx Frame Count. This counter increments for received good and bad frames. 0x0 R P1 Rx Broadcast Frame Count Register Address: 0xA1, Reset: 0x00000000, Name: P1_RX_BCAST_CNT Table 87. Bit Descriptions for P1_RX_BCAST_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_BCAST_CNT Rx Broadcast Frame Count. This counter increments for received good and bad frames. 0x0 R P1 Rx Multicast Frame Count Register Address: 0xA2, Reset: 0x00000000, Name: P1_RX_MCAST_CNT Table 88. Bit Descriptions for P1_RX_MCAST_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_MCAST_CNT Rx Multicast Frame Count. This counter increments for received good and bad frames. 0x0 R P1 Rx Unicast Frame Count Register Address: 0xA3, Reset: 0x00000000, Name: P1_RX_UCAST_CNT Table 89. Bit Descriptions for P1_RX_UCAST_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_UCAST_CNT Rx Unicast Frame Count. 0x0 R P1 Rx CRC Errored Frame Count Register Address: 0xA4, Reset: 0x00000000, Name: P1_RX_CRC_ERR_CNT Table 90. Bit Descriptions for P1_RX_CRC_ERR_CNT Bits Bit Name Description Reset Access [31:0] P1_RX_CRC_ERR_CNT Rx CRC Errored Frame Count. 0x0 R P1 Rx Align Error Count Register Address: 0xA5, Reset: 0x00000000, Name: P1_RX_ALGN_ERR_CNT |
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