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ADIN1110BCPZ-R7 数据表(PDF) 60 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 60 Page - Analog Devices |
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60 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 60 of 104 Table 80. Bit Descriptions for TS_TIMER_START Bits Bit Name Description Reset Access TS_TIMER starts, writing to TS_TIMER_STOP stops the timer and returns the TS_TIMER output to its default value. TS_CAPT Pin 0 Time Stamp Register Address: 0x89, Reset: 0x00000000, Name: TS_EXT_CAPT0 Time stamp captured on the assertion of the TS_CAPT pin. Table 81. Bit Descriptions for TS_EXT_CAPT0 Bits Bit Name Description Reset Access [31:0] TS_EXT_CAPTD, Bits[31:0] Time Stamp Captured on the Assertion of the TS_CAPT Pin. 0x0 R TS_CAPT Pin 1 Time Stamp Register Address: 0x8A, Reset: 0x00000000, Name: TS_EXT_CAPT1 Time stamp captured on the assertion of the TS_CAPT pin. Table 82. Bit Descriptions for TS_EXT_CAPT1 Bits Bit Name Description Reset Access [31:0] TS_EXT_CAPTD, Bits[63:32] Time stamp captured on the assertion of the TS_CAPT pin. 0x0 R TS_CAPT Free Running Counter Register Address: 0x8B, Reset: 0x00000000, Name: TS_FREECNT_CAPT Capture of the free running counter when TS_CAPT asserts. Table 83. Bit Descriptions for TS_FREECNT_CAPT Bits Bit Name Description Reset Access [31:0] TS_CNT_CAPTD Captured Free Running Counter. This 32-bit counter is captured on the assertion of TS_CAPT pin, as is TS_EXT_CAPT. 0x0 R P1 MAC Rx Frame Size Register Address: 0x90, Reset: 0x00000000, Name: P1_RX_FSIZE Table 84. Bit Descriptions for P1_RX_FSIZE Bits Bit Name Description Reset Access [31:11] RESERVED Reserved. 0x0 R [10:0] P1_RX_FRM_SIZE Receive Frame Size. The size of the frame at the head of the Rx FIFO in bytes. The size includes the appended header. When using the generic SPI protocol, this register must be read before reading a frame from a receive FIFO via P1_RX. 0x0 R P1 MAC Receive Register Address: 0x91, Reset: 0x00000000, Name: P1_RX The receive FIFO is read via this register. It is possible to burst read data from the Rx FIFO over SPI. |
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