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ADIN1110BCPZ-R7 数据表(PDF) 57 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 57 Page - Analog Devices |
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57 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 57 of 104 Table 68. Bit Descriptions for ADDR_FILT_UPRn Bits Bit Name Description Reset Access 1: apply to Port 1. Apply this table entry/rule to frames received on Port 1. [29:20] RESERVED Reserved. 0x0 R 19 HOST_PRI Host Rx Port Priority. On the receive port to the host, there are two FIFOs: low and high priority. This field determines which FIFO the frame is placed in. 0 = low priority, and 1 = high priority. By default, memory resources are provided for a high priority FIFO. However, if the memory assigned to the high priority FIFO is moved to another FIFO by writing to the FIFO_SIZE register, this field must not be set to 1. 0x0 R/W [18:17] RESERVED Reserved. 0x0 R 16 TO_HOST Forward Frames Matching This MAC Address to the Host. If APPLY2PORT1 is set to 1 and TO_HOST is 1, frames matching this DA are forwarded to the host. If TO_HOST is 0, frames matching the DA for this entry are dropped. 0x0 R/W [15:0] MAC_ADDR, Bits[47:32] MAC Address. 0x0 R/W MAC Address DA Filter Lower 32 Bits Registers Address: 0x51 to 0x6F (Increments of 2), Reset: 0x00000000, Name: ADDR_FILT_LWRn Contains the lower 32 bits of a MAC address in the DA filter table. A write to one of these registers must be preceded by a write to the corresponding ADDR_FILT_UPRn register. Table 69. Bit Descriptions for ADDR_FILT_LWRn Bits Bit Name Description Reset Access [31:0] MAC_ADDR, Bits[31:0] MAC Address. 0x0 R/W Upper 16 Bits of the MAC Address Mask Register Address: 0x70 to 0x72 (Increments of 2), Reset: 0x0000FFFF, Name: ADDR_MSK_UPRn The upper 16 bits of a MAC address mask in the DA mask table. When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. They must be written in order with the UPR register written first and the LWR register written last. Table 70. Bit Descriptions for ADDR_MSK_UPRn Bits Bit Name Description Reset Access [31:16] RESERVED Reserved. 0x0 R [15:0] MAC_ADDR_MASK, Bits[47:32] MAC Address Bit Mask for the Address Table. 0xFFFF R/W Lower 32 Bits of the MAC Address Mask Register Address: 0x71 to 0x73 (Increments of 2), Reset: 0xFFFFFFFF, Name: ADDR_MSK_LWRn The lower 32 bits of a MAC address mask in the DA mask table. When writing the ADDR_MSK_x registers, all two register locations must be written in order for a given table entry. The register locations must be written in order with the UPR register written first and the LWR register written last. Table 71. Bit Descriptions for ADDR_MSK_LWRn Bits Bit Name Description Reset Access [31:0] MAC_ADDR_MASK, Bits[31:0] MAC Address Bit Mask for the Address Table. 0xFFFFFFFF R/W |
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