ADIN1110BCPZ-R7 datasheet(39/104 Pages) AD

39 / 104 page

Data Sheet

ADIN1110

MAC SPI

analog.com

Rev. 0 | 39 of 104

Statistics Counters

There are 15 32-bit counters on the receive port that increment on

each frame transmit and receive.

Table 32. Statistics Counters

Name

Description

P1_RX_FRM_CNT

Rx frame count

P1_RX_UCAST_CNT

Rx unicast frame count

P1_RX_MCAST_CNT

Rx multicast frame count

P1_RX_BCAST_CNT

Rx broadcast frame count

P1_RX_CRC_ERR_CNT

Rx CRC errored frame count

P1_RX_ALGN_ERR_CNT

Rx alignment error count

P1_RX_PHY_ERR_CNT

Rx PHY error count

P1_RX_LS_ERR_CNT

Rx long and short frame error count

P1_TX_FRM_CNT

Tx frame count

P1_TX_UCAST_CNT

Tx unicast frame count

P1_TX_MCAST_CNT

Tx multicast frame count

P1_TX_BCAST_CNT

Tx broadcast frame count

P1_RX_DROP_FULL_CNT

Rx frames dropped due to FIFO full

P1_RX_DROP_FILT_CNT

Rx frames dropped due to filtering

P1_RX_IFG_ERR_CNT

Rx frames received with interframe gap (IFG)

errors

Receive Drop FIFO Full Counter

Before the first byte of a received frame is written into the appropri-

ate receive FIFO, the space in the FIFO is checked. If there is

no space for at least 256 bytes, the frame is dropped and the

P1_RX_DROP_FULL_CNT counter increments. If there is space

for at least 256 bytes in the FIFO, the logic commences writing

the frame to the receive FIFO. If the received frame exceeds 256

bytes and the receive FIFO fills, the frame is dropped and the

P1_RX_DROP_FULL_CNT counter increments.

Frame Receive and Transmit Errors

By default, all received errored frames are dropped and counted.

Received errored frames do not generate interrupts. Instead, they

are dropped and counted, and the software must monitor the

statistics counters.

SRAM ECC Error

When writing a frame to the FIFO, the size of the frame is inserted

in a 16-bit word at the front of the frame and written to the FIFO. A

5-bit error correction code (ECC) is placed alongside the size field.

When this location is read from static random-access memory

(SRAM), the ECC is checked. If a double bit error is detected,

the RX_ECC_ERR or TX_ECC_ERR bits of the STATUS1 register

assert. If a double bit error is detected on reading a frame header

from the receive FIFO, the frame is not transmitted.

In response to an ECC error, a FIFO automatically clears. All

frames in the FIFO are lost, transmission stops, and a bad CRC

is appended to the frame that was transmitted. The next frame

received is written to a FIFO.

SPI ACCESS TO THE PHY REGISTERS

The ADIN1110 provides indirect access using the SPI to access the

PHY management registers. The 8 registers MDIOACCn in the SPI

Each MDIOACCn register corresponds to an MDIO transaction.

The MDC default speed is 2.5 MHz. Either 2.5 MHz or 4.166

MHz MDC frequency can be selected via the MSPEED bits in the

CONFIG2 register.

The MDIO master polls in round robin mode the TRDONE bits of

the eight MDIOACCn registers. When the MDIO master detects that

one of the TRDONE fields is 0, an MDIO transaction is started

by the MDIO master. When the MDIO transaction completes, the

TRDONE bits are set to 1, and the master proceeds to check the

TRDONE bits of the next MDIOACCn register.

Note that MDIO_DEVAD is always written with the device ID of the

and MDIO_ST is written to 0x0 for Clause 45 access (this applies to

all of the following examples).

Example write to PHY Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Regis-

ter XYZ, MDIO_DEVAD = the device ID of Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x0(ADDR), MDIO_ST =

0x0, and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Optionally, poll MDIOACC0.TRDONE = 0x1 to determine that

the write address operation has completed.

4. Poll MDIOACC1.TRDONE = 0x1 to determine that the write

data operation has completed.

Example read of PHY Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of Register

XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_OP = 0x3(RD) and TRDONE =

0x0.

3. Poll MDIOACC1. TRDONE= 0x1 to determine that the write da-

ta operation has completed. MDIOACC1. MDIO_DATA reflects

the content of MDIO Register XYZ.

Example write operation followed by a read to verify the write

operation:

1. Write MDIOACC0 with MDIO_DATA = the address of register

ABC and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DATA = the value to be written to

3. Write MDIOACC2 MDIO_OP = 0x3(RD) and TRDONE = 0x0.

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