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ADIN1110BCPZ-R7 数据表(PDF) 75 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 75 Page - Analog Devices |
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75 / 104 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. 0 | 75 of 104 Table 128. Bit Descriptions for PMA_PMD_BT1_CONTROL Bits Bit Name Description Reset Access [3:0] BT1_TYPE_SEL BASE-T1 Type Selection. See IEEE Standard 802.3 for the following control register bit definitions (where X means don't care): 0x2 R/W 1XXX: reserved. 01XX: reserved. 0011: 10BASE-T1S. 0010: 10BASE-T1L. 0001: 1000BASE-T. 0000: 100BASE-T. BT1_TYPE_SEL is used only when autonegotiation is disabled and forced link configuration mode is enabled. If autonegotiation is enabled, the PHY type is determined by the autonegotiation process itself. Note that for ADIN1110, the only valid value is for 10BASE-T1L. 10BASE-T1L PMA Control Register Device Address: 0x01; Register Address: 0x08F6, Reset: 0x0000, Name: B10L_PMA_CNTRL This address corresponds to the 10BASE-T1L PMA control register specified in Clause 45.2.1.186a of Standard 802.3cg. Table 129. Bit Descriptions for B10L_PMA_CNTRL Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x0 R/W SC 14 B10L_TX_DIS_MODE_EN 10BASE-T1L Transmit Disable Mode. When this bit is set to 1, it disables output on the transmit path. Otherwise, it enables output on the transmit path. 0x0 R/W 13 RESERVED Reserved. 0x0 R 12 B10L_TX_LVL_HI 10BASE-T1L Transmit Voltage Amplitude Control. This configuration is only used when autonegotiation is disabled. Otherwise, the configuration is decided by the autonegotiation process. When this bit is set as 1, the device works in the 2.4 V p-p operating mode. Otherwise, the device works in the 1.0 V p-p operating mode. Pin Dependent R/W 11 RESERVED Reserved. 0x0 R/W 10 B10L_EEE 10BASE-T1L EEE Enable. 0x0 R/W [9:1] RESERVED Reserved. 0x0 R 0 B10L_LB_PMA_LOC_EN 10BASE-T1L PMA Loopback. When this bit is set to 1, the PMA accepts data on the transmit path and returns it on the receive path. When this bit is set to 0, the PMA works in normal mode. 0x0 R/W 10BASE-T1L PMA Status Register Device Address: 0x01; Register Address: 0x08F7, Reset: 0x2800, Name: B10L_PMA_STAT This address corresponds to the 10BASE-T1L PMA status register specified in Clause 45.2.1.186b of Standard 802.3cg. Table 130. Bit Descriptions for B10L_PMA_STAT Bits Bit Name Description Reset Access [15:14] RESERVED Reserved. 0x0 R 13 B10L_LB_PMA_LOC_ABLE 10BASE-T1L PMA Loopback Ability. This bit always reads as 1 because the PMA has loopback ability 0x1 R 12 B10L_TX_LVL_HI_ABLE 10BASE-T1L High Voltage Tx Ability. Indicates that the PHY supports 10BASE-T1L high voltage (2.4 V p-p) transmit level operating mode. Pin Dependent R 11 B10L_PMA_SFT_PD_ABLE PMA Supports Power-Down. Indicates that the PMA supports software power-down. 0x1 R 10 B10L_EEE_ABLE 10BASE-T1L EEE Ability. Indicates if the PHY supports 10BASE-T1L EEE. 0x0 R |
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